2021-03-31 17:52:26 +00:00
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#include "cc1101.h"
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#include <assert.h>
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#include <string.h>
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2021-11-30 12:09:43 +00:00
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CC1101Status cc1101_strobe(FuriHalSpiBusHandle* handle, uint8_t strobe) {
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2022-01-05 16:10:18 +00:00
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uint8_t tx[1] = {strobe};
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CC1101Status rx[1] = {0};
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2021-03-31 17:52:26 +00:00
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2022-03-30 15:23:40 +00:00
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while(furi_hal_gpio_read(handle->miso))
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2022-01-05 16:10:18 +00:00
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;
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2021-11-30 12:09:43 +00:00
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furi_hal_spi_bus_trx(handle, tx, (uint8_t*)rx, 1, CC1101_TIMEOUT);
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2021-03-31 17:52:26 +00:00
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assert(rx[0].CHIP_RDYn == 0);
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return rx[0];
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}
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2021-11-30 12:09:43 +00:00
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CC1101Status cc1101_write_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t data) {
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2022-01-05 16:10:18 +00:00
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uint8_t tx[2] = {reg, data};
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CC1101Status rx[2] = {0};
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2021-03-31 17:52:26 +00:00
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2022-03-30 15:23:40 +00:00
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while(furi_hal_gpio_read(handle->miso))
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2022-01-05 16:10:18 +00:00
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;
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2021-11-30 12:09:43 +00:00
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furi_hal_spi_bus_trx(handle, tx, (uint8_t*)rx, 2, CC1101_TIMEOUT);
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2021-03-31 17:52:26 +00:00
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2021-12-01 15:44:39 +00:00
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assert((rx[0].CHIP_RDYn | rx[1].CHIP_RDYn) == 0);
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2021-03-31 17:52:26 +00:00
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return rx[1];
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}
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2021-11-30 12:09:43 +00:00
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CC1101Status cc1101_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* data) {
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2021-03-31 17:52:26 +00:00
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assert(sizeof(CC1101Status) == 1);
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2021-12-01 15:44:39 +00:00
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uint8_t tx[2] = {reg | CC1101_READ, 0};
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CC1101Status rx[2] = {0};
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2021-03-31 17:52:26 +00:00
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2022-03-30 15:23:40 +00:00
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while(furi_hal_gpio_read(handle->miso))
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2022-01-05 16:10:18 +00:00
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;
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2021-11-30 12:09:43 +00:00
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furi_hal_spi_bus_trx(handle, tx, (uint8_t*)rx, 2, CC1101_TIMEOUT);
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2021-03-31 17:52:26 +00:00
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assert((rx[0].CHIP_RDYn) == 0);
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*data = *(uint8_t*)&rx[1];
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return rx[0];
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}
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2021-11-30 12:09:43 +00:00
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uint8_t cc1101_get_partnumber(FuriHalSpiBusHandle* handle) {
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2022-01-05 16:10:18 +00:00
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uint8_t partnumber = 0;
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cc1101_read_reg(handle, CC1101_STATUS_PARTNUM | CC1101_BURST, &partnumber);
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2021-03-31 17:52:26 +00:00
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return partnumber;
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}
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2021-11-30 12:09:43 +00:00
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uint8_t cc1101_get_version(FuriHalSpiBusHandle* handle) {
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2022-01-05 16:10:18 +00:00
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uint8_t version = 0;
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cc1101_read_reg(handle, CC1101_STATUS_VERSION | CC1101_BURST, &version);
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2021-03-31 17:52:26 +00:00
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return version;
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}
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2021-11-30 12:09:43 +00:00
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uint8_t cc1101_get_rssi(FuriHalSpiBusHandle* handle) {
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2022-01-05 16:10:18 +00:00
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uint8_t rssi = 0;
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cc1101_read_reg(handle, CC1101_STATUS_RSSI | CC1101_BURST, &rssi);
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2021-03-31 17:52:26 +00:00
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return rssi;
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_reset(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SRES);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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CC1101Status cc1101_get_status(FuriHalSpiBusHandle* handle) {
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return cc1101_strobe(handle, CC1101_STROBE_SNOP);
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2021-06-08 09:51:16 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_shutdown(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SPWD);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_calibrate(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SCAL);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_switch_to_idle(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SIDLE);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_switch_to_rx(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SRX);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_switch_to_tx(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_STX);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_flush_rx(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SFRX);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_flush_tx(FuriHalSpiBusHandle* handle) {
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cc1101_strobe(handle, CC1101_STROBE_SFTX);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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uint32_t cc1101_set_frequency(FuriHalSpiBusHandle* handle, uint32_t value) {
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2021-06-29 21:19:20 +00:00
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uint64_t real_value = (uint64_t)value * CC1101_FDIV / CC1101_QUARTZ;
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2021-03-31 17:52:26 +00:00
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// Sanity check
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2021-06-29 21:19:20 +00:00
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assert((real_value & CC1101_FMASK) == real_value);
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2021-03-31 17:52:26 +00:00
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2021-11-30 12:09:43 +00:00
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cc1101_write_reg(handle, CC1101_FREQ2, (real_value >> 16) & 0xFF);
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2022-01-05 16:10:18 +00:00
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cc1101_write_reg(handle, CC1101_FREQ1, (real_value >> 8) & 0xFF);
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cc1101_write_reg(handle, CC1101_FREQ0, (real_value >> 0) & 0xFF);
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2021-03-31 17:52:26 +00:00
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2021-06-29 21:19:20 +00:00
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uint64_t real_frequency = real_value * CC1101_QUARTZ / CC1101_FDIV;
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2021-03-31 17:52:26 +00:00
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return (uint32_t)real_frequency;
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}
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2021-11-30 12:09:43 +00:00
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uint32_t cc1101_set_intermediate_frequency(FuriHalSpiBusHandle* handle, uint32_t value) {
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2021-06-29 21:19:20 +00:00
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uint64_t real_value = value * CC1101_IFDIV / CC1101_QUARTZ;
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2021-03-31 17:52:26 +00:00
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assert((real_value & 0xFF) == real_value);
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2022-01-05 16:10:18 +00:00
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cc1101_write_reg(handle, CC1101_FSCTRL0, (real_value >> 0) & 0xFF);
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2021-03-31 17:52:26 +00:00
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2021-06-29 21:19:20 +00:00
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uint64_t real_frequency = real_value * CC1101_QUARTZ / CC1101_IFDIV;
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2021-03-31 17:52:26 +00:00
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return (uint32_t)real_frequency;
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}
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2021-11-30 12:09:43 +00:00
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void cc1101_set_pa_table(FuriHalSpiBusHandle* handle, const uint8_t value[8]) {
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2022-12-26 12:13:30 +00:00
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uint8_t tx[9] = {CC1101_PATABLE | CC1101_BURST}; //-V1009
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2022-01-05 16:10:18 +00:00
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CC1101Status rx[9] = {0};
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2021-03-31 17:52:26 +00:00
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memcpy(&tx[1], &value[0], 8);
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2022-03-30 15:23:40 +00:00
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while(furi_hal_gpio_read(handle->miso))
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2022-01-05 16:10:18 +00:00
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;
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2021-11-30 12:09:43 +00:00
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furi_hal_spi_bus_trx(handle, tx, (uint8_t*)rx, sizeof(rx), CC1101_TIMEOUT);
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2021-03-31 17:52:26 +00:00
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2021-12-01 15:44:39 +00:00
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assert((rx[0].CHIP_RDYn | rx[8].CHIP_RDYn) == 0);
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2021-03-31 17:52:26 +00:00
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}
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2021-11-30 12:09:43 +00:00
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uint8_t cc1101_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* data, uint8_t size) {
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2021-06-08 09:51:16 +00:00
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uint8_t buff_tx[64];
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uint8_t buff_rx[64];
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buff_tx[0] = CC1101_FIFO | CC1101_BURST;
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memcpy(&buff_tx[1], data, size);
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2021-03-31 17:52:26 +00:00
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// Start transaction
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// Wait IC to become ready
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2022-03-30 15:23:40 +00:00
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while(furi_hal_gpio_read(handle->miso))
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2022-01-05 16:10:18 +00:00
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;
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2021-03-31 17:52:26 +00:00
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// Tell IC what we want
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2022-01-05 16:10:18 +00:00
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furi_hal_spi_bus_trx(handle, buff_tx, (uint8_t*)buff_rx, size + 1, CC1101_TIMEOUT);
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2021-03-31 17:52:26 +00:00
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return size;
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}
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2021-11-30 12:09:43 +00:00
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uint8_t cc1101_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* data, uint8_t* size) {
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2021-06-08 09:51:16 +00:00
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uint8_t buff_tx[64];
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buff_tx[0] = CC1101_FIFO | CC1101_READ | CC1101_BURST;
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uint8_t buff_rx[2];
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// Start transaction
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// Wait IC to become ready
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2022-03-30 15:23:40 +00:00
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while(furi_hal_gpio_read(handle->miso))
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2022-01-05 16:10:18 +00:00
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;
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2021-06-08 09:51:16 +00:00
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// First byte - packet length
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2021-11-30 12:09:43 +00:00
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furi_hal_spi_bus_trx(handle, buff_tx, buff_rx, 2, CC1101_TIMEOUT);
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2021-12-01 15:44:39 +00:00
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// Check that the packet is placed in the receive buffer
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if(buff_rx[1] > 64) {
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*size = 64;
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} else {
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*size = buff_rx[1];
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}
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2021-11-30 12:09:43 +00:00
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furi_hal_spi_bus_trx(handle, &buff_tx[1], data, *size, CC1101_TIMEOUT);
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2021-06-08 09:51:16 +00:00
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return *size;
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2021-03-31 17:52:26 +00:00
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}
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