2021-08-08 18:03:25 +00:00
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#include "furi-hal-interrupt.h"
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2021-06-29 21:19:20 +00:00
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#include <furi.h>
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#include <main.h>
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#include <stm32wbxx_ll_tim.h>
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2021-08-08 18:03:25 +00:00
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volatile FuriHalInterruptISR furi_hal_tim_tim2_isr = NULL;
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volatile FuriHalInterruptISR furi_hal_tim_tim1_isr = NULL;
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2021-06-29 21:19:20 +00:00
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2021-08-08 18:03:25 +00:00
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#define FURI_HAL_INTERRUPT_DMA_COUNT 2
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#define FURI_HAL_INTERRUPT_DMA_CHANNELS_COUNT 8
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2021-07-15 13:54:11 +00:00
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2021-08-08 18:03:25 +00:00
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volatile FuriHalInterruptISR furi_hal_dma_channel_isr[FURI_HAL_INTERRUPT_DMA_COUNT][FURI_HAL_INTERRUPT_DMA_CHANNELS_COUNT] = {0};
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2021-07-15 13:54:11 +00:00
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2021-08-08 18:03:25 +00:00
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void furi_hal_interrupt_init() {
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2021-07-30 10:13:18 +00:00
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NVIC_SetPriority(RCC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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NVIC_EnableIRQ(RCC_IRQn);
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NVIC_SetPriority(TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
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2021-07-15 13:54:11 +00:00
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NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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2021-07-30 10:13:18 +00:00
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2021-07-28 08:45:42 +00:00
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FURI_LOG_I("FuriHalInterrupt", "Init OK");
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2021-06-29 21:19:20 +00:00
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}
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2021-08-08 18:03:25 +00:00
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void furi_hal_interrupt_set_timer_isr(TIM_TypeDef* timer, FuriHalInterruptISR isr) {
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2021-06-29 21:19:20 +00:00
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if (timer == TIM2) {
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if (isr) {
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2021-08-08 18:03:25 +00:00
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furi_assert(furi_hal_tim_tim2_isr == NULL);
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2021-06-29 21:19:20 +00:00
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} else {
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2021-08-08 18:03:25 +00:00
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furi_assert(furi_hal_tim_tim2_isr != NULL);
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2021-06-29 21:19:20 +00:00
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}
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2021-08-08 18:03:25 +00:00
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furi_hal_tim_tim2_isr = isr;
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2021-08-05 21:11:35 +00:00
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} else if (timer == TIM1) {
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if (isr) {
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2021-08-08 18:03:25 +00:00
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furi_assert(furi_hal_tim_tim1_isr == NULL);
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2021-08-05 21:11:35 +00:00
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} else {
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2021-08-08 18:03:25 +00:00
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furi_assert(furi_hal_tim_tim1_isr != NULL);
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2021-08-05 21:11:35 +00:00
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}
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2021-08-08 18:03:25 +00:00
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furi_hal_tim_tim1_isr = isr;
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2021-06-29 21:19:20 +00:00
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} else {
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2021-09-15 09:59:49 +00:00
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furi_crash(NULL);
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2021-06-29 21:19:20 +00:00
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}
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}
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2021-08-08 18:03:25 +00:00
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void furi_hal_interrupt_set_dma_channel_isr(DMA_TypeDef* dma, uint32_t channel, FuriHalInterruptISR isr) {
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2021-07-30 10:13:18 +00:00
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--channel; // Pascal
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2021-07-15 13:54:11 +00:00
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furi_check(dma);
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2021-08-08 18:03:25 +00:00
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furi_check(channel < FURI_HAL_INTERRUPT_DMA_CHANNELS_COUNT);
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2021-07-15 13:54:11 +00:00
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if (dma == DMA1) {
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2021-08-08 18:03:25 +00:00
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furi_hal_dma_channel_isr[0][channel] = isr;
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2021-08-05 21:11:35 +00:00
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} else if (dma == DMA2) {
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2021-08-08 18:03:25 +00:00
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furi_hal_dma_channel_isr[1][channel] = isr;
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2021-07-15 13:54:11 +00:00
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} else {
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2021-09-15 09:59:49 +00:00
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furi_crash(NULL);
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2021-07-15 13:54:11 +00:00
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}
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}
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2021-06-29 21:19:20 +00:00
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extern void api_interrupt_call(InterruptType type, void* hw);
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/* ST HAL symbols */
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/* Comparator trigger event */
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void HAL_COMP_TriggerCallback(COMP_HandleTypeDef* hcomp) {
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api_interrupt_call(InterruptTypeComparatorTrigger, hcomp);
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}
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/* Timer update event */
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void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef* htim) {
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api_interrupt_call(InterruptTypeTimerUpdate, htim);
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}
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2021-07-15 13:54:11 +00:00
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/* Timer 2 */
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void TIM2_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_tim_tim2_isr) {
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furi_hal_tim_tim2_isr();
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2021-07-15 13:54:11 +00:00
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} else {
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HAL_TIM_IRQHandler(&htim2);
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}
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}
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2021-08-05 21:11:35 +00:00
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/* Timer 1 Update */
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void TIM1_UP_TIM16_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_tim_tim1_isr) {
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furi_hal_tim_tim1_isr();
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2021-08-05 21:11:35 +00:00
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} else {
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HAL_TIM_IRQHandler(&htim1);
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}
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}
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2021-07-15 13:54:11 +00:00
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/* DMA 1 */
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void DMA1_Channel1_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][0]) furi_hal_dma_channel_isr[0][0]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel2_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][1]) furi_hal_dma_channel_isr[0][1]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel3_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][2]) furi_hal_dma_channel_isr[0][2]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel4_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][3]) furi_hal_dma_channel_isr[0][3]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel5_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][4]) furi_hal_dma_channel_isr[0][4]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel6_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][5]) furi_hal_dma_channel_isr[0][5]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel7_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][6]) furi_hal_dma_channel_isr[0][6]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA1_Channel8_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[0][7]) furi_hal_dma_channel_isr[0][7]();
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2021-07-15 13:54:11 +00:00
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}
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/* DMA 2 */
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void DMA2_Channel1_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][0]) furi_hal_dma_channel_isr[1][0]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel2_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][1]) furi_hal_dma_channel_isr[1][1]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel3_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][2]) furi_hal_dma_channel_isr[1][2]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel4_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][3]) furi_hal_dma_channel_isr[1][3]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel5_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][4]) furi_hal_dma_channel_isr[1][4]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel6_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][5]) furi_hal_dma_channel_isr[1][5]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel7_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][6]) furi_hal_dma_channel_isr[1][6]();
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2021-07-15 13:54:11 +00:00
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}
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void DMA2_Channel8_IRQHandler(void) {
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2021-08-08 18:03:25 +00:00
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if (furi_hal_dma_channel_isr[1][7]) furi_hal_dma_channel_isr[1][7]();
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2021-07-15 13:54:11 +00:00
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}
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2021-07-30 10:13:18 +00:00
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void TAMP_STAMP_LSECSS_IRQHandler(void) {
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if (LL_RCC_IsActiveFlag_LSECSS()) {
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LL_RCC_ClearFlag_LSECSS();
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if (!LL_RCC_LSE_IsReady()) {
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FURI_LOG_E("FuriHalInterrupt", "LSE CSS fired: resetting system");
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NVIC_SystemReset();
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} else {
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FURI_LOG_E("FuriHalInterrupt", "LSE CSS fired: but LSE is alive");
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}
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}
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}
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void RCC_IRQHandler(void) {
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}
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void NMI_Handler(void) {
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if (LL_RCC_IsActiveFlag_HSECSS()) {
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LL_RCC_ClearFlag_HSECSS();
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FURI_LOG_E("FuriHalInterrupt", "HSE CSS fired: resetting system");
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NVIC_SystemReset();
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}
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}
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void HardFault_Handler(void) {
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if ((*(volatile uint32_t *)CoreDebug_BASE) & (1 << 0)) {
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__asm("bkpt 1");
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}
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while (1) {}
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}
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void MemManage_Handler(void) {
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__asm("bkpt 1");
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while (1) {}
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}
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void BusFault_Handler(void) {
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__asm("bkpt 1");
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while (1) {}
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}
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void UsageFault_Handler(void) {
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__asm("bkpt 1");
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while (1) {}
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}
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void DebugMon_Handler(void) {
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}
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