2021-09-10 02:19:02 +00:00
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#include <furi-hal-bt.h>
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#include <ble.h>
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#include <stm32wbxx.h>
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#include <shci.h>
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#include <cmsis_os2.h>
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2021-10-12 16:41:42 +00:00
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#include <furi.h>
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2021-09-10 02:19:02 +00:00
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2021-11-04 17:26:41 +00:00
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osMutexId_t furi_hal_bt_core2_mtx = NULL;
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2021-09-10 02:19:02 +00:00
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void furi_hal_bt_init() {
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2021-11-04 17:26:41 +00:00
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furi_hal_bt_core2_mtx = osMutexNew(NULL);
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}
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static bool furi_hal_bt_wait_startup() {
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uint16_t counter = 0;
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while (!(ble_glue_get_status() == BleGlueStatusStarted || ble_glue_get_status() == BleGlueStatusBleStackMissing)) {
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osDelay(10);
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counter++;
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if (counter > 1000) {
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return false;
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}
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}
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return true;
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}
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bool furi_hal_bt_start_core2() {
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furi_assert(furi_hal_bt_core2_mtx);
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bool ret = false;
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osMutexAcquire(furi_hal_bt_core2_mtx, osWaitForever);
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2021-09-10 02:19:02 +00:00
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// Explicitly tell that we are in charge of CLK48 domain
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HAL_HSEM_FastTake(CFG_HW_CLK48_CONFIG_SEMID);
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2021-11-04 17:26:41 +00:00
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// Start Core2
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ble_glue_init();
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// Wait for Core2 start
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ret = furi_hal_bt_wait_startup();
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osMutexRelease(furi_hal_bt_core2_mtx);
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return ret;
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2021-09-10 02:19:02 +00:00
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}
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2021-10-12 16:41:42 +00:00
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bool furi_hal_bt_init_app(BleEventCallback event_cb, void* context) {
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furi_assert(event_cb);
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return gap_init(event_cb, context);
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2021-09-10 02:19:02 +00:00
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}
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2021-09-15 16:58:32 +00:00
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void furi_hal_bt_start_advertising() {
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if(gap_get_state() == GapStateIdle) {
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gap_start_advertising();
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}
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}
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void furi_hal_bt_stop_advertising() {
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2021-09-16 16:12:07 +00:00
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if(furi_hal_bt_is_active()) {
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2021-09-15 16:58:32 +00:00
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gap_stop_advertising();
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2021-09-21 09:48:08 +00:00
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while(furi_hal_bt_is_active()) {
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osDelay(1);
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}
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2021-09-15 16:58:32 +00:00
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}
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}
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2021-10-12 16:41:42 +00:00
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void furi_hal_bt_set_data_event_callbacks(SerialSvcDataReceivedCallback on_received_cb, SerialSvcDataSentCallback on_sent_cb, void* context) {
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serial_svc_set_callbacks(on_received_cb, on_sent_cb, context);
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}
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bool furi_hal_bt_tx(uint8_t* data, uint16_t size) {
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if(size > FURI_HAL_BT_PACKET_SIZE_MAX) {
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return false;
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}
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return serial_svc_update_tx(data, size);
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}
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2021-11-04 17:26:41 +00:00
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bool furi_hal_bt_get_key_storage_buff(uint8_t** key_buff_addr, uint16_t* key_buff_size) {
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bool ret = false;
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BleGlueStatus status = ble_glue_get_status();
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if(status == BleGlueStatusUninitialized || BleGlueStatusStarted) {
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ble_app_get_key_storage_buff(key_buff_addr, key_buff_size);
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ret = true;
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}
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return ret;
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}
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void furi_hal_bt_set_key_storage_change_callback(BleGlueKeyStorageChangedCallback callback, void* context) {
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furi_assert(callback);
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ble_glue_set_key_storage_changed_callback(callback, context);
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}
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void furi_hal_bt_nvm_sram_sem_acquire() {
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while(HAL_HSEM_FastTake(CFG_HW_BLE_NVM_SRAM_SEMID) != HAL_OK) {
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osDelay(1);
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}
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}
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void furi_hal_bt_nvm_sram_sem_release() {
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HAL_HSEM_Release(CFG_HW_BLE_NVM_SRAM_SEMID, 0);
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}
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2021-09-10 02:19:02 +00:00
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void furi_hal_bt_dump_state(string_t buffer) {
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2021-11-04 17:26:41 +00:00
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BleGlueStatus status = ble_glue_get_status();
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2021-09-10 02:19:02 +00:00
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if (status == BleGlueStatusStarted) {
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uint8_t HCI_Version;
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uint16_t HCI_Revision;
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uint8_t LMP_PAL_Version;
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uint16_t Manufacturer_Name;
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uint16_t LMP_PAL_Subversion;
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tBleStatus ret = hci_read_local_version_information(
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&HCI_Version, &HCI_Revision, &LMP_PAL_Version, &Manufacturer_Name, &LMP_PAL_Subversion
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);
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string_cat_printf(buffer,
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"Ret: %d, HCI_Version: %d, HCI_Revision: %d, LMP_PAL_Version: %d, Manufacturer_Name: %d, LMP_PAL_Subversion: %d",
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ret, HCI_Version, HCI_Revision, LMP_PAL_Version, Manufacturer_Name, LMP_PAL_Subversion
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);
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} else {
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string_cat_printf(buffer, "BLE not ready");
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}
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}
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bool furi_hal_bt_is_alive() {
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2021-11-04 17:26:41 +00:00
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BleGlueStatus status = ble_glue_get_status();
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return (status == BleGlueStatusBleStackMissing) || (status == BleGlueStatusStarted);
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2021-09-16 16:12:07 +00:00
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}
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bool furi_hal_bt_is_active() {
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2021-09-15 16:58:32 +00:00
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return gap_get_state() > GapStateIdle;
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2021-09-10 02:19:02 +00:00
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}
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2021-11-04 17:26:41 +00:00
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static void furi_hal_bt_lock_flash_core2(bool erase_flag) {
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// Take flash controller ownership
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2021-09-15 14:40:09 +00:00
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while (HAL_HSEM_FastTake(CFG_HW_FLASH_SEMID) != HAL_OK) {
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2021-11-04 17:26:41 +00:00
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taskYIELD();
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2021-09-10 02:19:02 +00:00
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}
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2021-09-16 16:12:07 +00:00
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2021-11-04 17:26:41 +00:00
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// Unlock flash operation
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2021-09-15 14:40:09 +00:00
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HAL_FLASH_Unlock();
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2021-11-04 17:26:41 +00:00
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// Erase activity notification
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2021-09-16 16:12:07 +00:00
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if(erase_flag) SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON);
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2021-11-04 17:26:41 +00:00
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while(true) {
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// Wait till flash controller become usable
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while(LL_FLASH_IsActiveFlag_OperationSuspended()) {
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taskYIELD();
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};
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2021-09-16 16:12:07 +00:00
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2021-11-04 17:26:41 +00:00
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// Just a little more love
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taskENTER_CRITICAL();
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2021-09-15 14:40:09 +00:00
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2021-11-04 17:26:41 +00:00
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// Actually we already have mutex for it, but specification is specification
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if (HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID)) {
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taskEXIT_CRITICAL();
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continue;
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}
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// Take sempahopre and prevent core2 from anyting funky
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if (HAL_HSEM_FastTake(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) != HAL_OK) {
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taskEXIT_CRITICAL();
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continue;
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}
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break;
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}
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2021-09-10 02:19:02 +00:00
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}
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2021-11-04 17:26:41 +00:00
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void furi_hal_bt_lock_flash(bool erase_flag) {
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// Acquire dangerous ops mutex
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osMutexAcquire(furi_hal_bt_core2_mtx, osWaitForever);
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// If Core2 is running use IPC locking
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BleGlueStatus status = ble_glue_get_status();
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if(status == BleGlueStatusStarted || status == BleGlueStatusBleStackMissing) {
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furi_hal_bt_lock_flash_core2(erase_flag);
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} else {
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HAL_FLASH_Unlock();
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}
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}
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static void furi_hal_bt_unlock_flash_core2(bool erase_flag) {
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// Funky ops are ok at this point
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, 0);
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// Task switching is ok
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taskEXIT_CRITICAL();
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2021-09-16 16:12:07 +00:00
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2021-11-04 17:26:41 +00:00
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// Doesn't make much sense, does it?
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while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
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taskYIELD();
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}
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// Erase activity over, core2 can continue
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2021-09-16 16:12:07 +00:00
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if(erase_flag) SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF);
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2021-11-04 17:26:41 +00:00
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// Lock flash controller
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2021-09-15 14:40:09 +00:00
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HAL_FLASH_Lock();
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2021-09-16 16:12:07 +00:00
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2021-11-04 17:26:41 +00:00
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// Release flash controller ownership
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HAL_HSEM_Release(CFG_HW_FLASH_SEMID, 0);
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}
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void furi_hal_bt_unlock_flash(bool erase_flag) {
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// If Core2 is running use IPC locking
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BleGlueStatus status = ble_glue_get_status();
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if(status == BleGlueStatusStarted || status == BleGlueStatusBleStackMissing) {
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furi_hal_bt_unlock_flash_core2(erase_flag);
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} else {
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HAL_FLASH_Lock();
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}
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// Release dangerous ops mutex
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osMutexRelease(furi_hal_bt_core2_mtx);
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2021-09-10 02:19:02 +00:00
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}
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void furi_hal_bt_start_tone_tx(uint8_t channel, uint8_t power) {
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aci_hal_set_tx_power_level(0, power);
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aci_hal_tone_start(channel, 0);
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}
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void furi_hal_bt_stop_tone_tx() {
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aci_hal_tone_stop();
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}
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void furi_hal_bt_start_packet_tx(uint8_t channel, uint8_t pattern, uint8_t datarate) {
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hci_le_enhanced_transmitter_test(channel, 0x25, pattern, datarate);
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}
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void furi_hal_bt_start_packet_rx(uint8_t channel, uint8_t datarate) {
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hci_le_enhanced_receiver_test(channel, datarate, 0);
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}
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uint16_t furi_hal_bt_stop_packet_test() {
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uint16_t num_of_packets = 0;
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hci_le_test_end(&num_of_packets);
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return num_of_packets;
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}
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void furi_hal_bt_start_rx(uint8_t channel) {
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aci_hal_rx_start(channel);
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}
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float furi_hal_bt_get_rssi() {
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float val;
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uint8_t rssi_raw[3];
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if (aci_hal_read_raw_rssi(rssi_raw) != BLE_STATUS_SUCCESS) {
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return 0.0f;
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}
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// Some ST magic with rssi
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uint8_t agc = rssi_raw[2] & 0xFF;
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int rssi = (((int)rssi_raw[1] << 8) & 0xFF00) + (rssi_raw[0] & 0xFF);
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if(rssi == 0 || agc > 11) {
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val = -127.0;
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} else {
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val = agc * 6.0f - 127.0f;
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while(rssi > 30) {
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val += 6.0;
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rssi >>=1;
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}
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val += (417 * rssi + 18080) >> 10;
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}
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return val;
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}
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uint32_t furi_hal_bt_get_transmitted_packets() {
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uint32_t packets = 0;
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aci_hal_le_tx_test_packet_number(&packets);
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return packets;
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}
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void furi_hal_bt_stop_rx() {
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aci_hal_rx_stop();
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}
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