2022-05-24 14:00:15 +00:00
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#include "digital_signal.h"
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#include <furi.h>
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#include <stm32wbxx_ll_dma.h>
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#include <stm32wbxx_ll_tim.h>
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#include <math.h>
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2022-07-03 14:51:50 +00:00
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#pragma GCC optimize("O3,unroll-loops,Ofast")
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2022-05-24 14:00:15 +00:00
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#define F_TIM (64000000.0)
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2022-07-03 14:51:50 +00:00
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#define T_TIM 1562 //15.625 ns *100
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#define T_TIM_DIV2 781 //15.625 ns / 2 *100
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2022-05-24 14:00:15 +00:00
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DigitalSignal* digital_signal_alloc(uint32_t max_edges_cnt) {
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DigitalSignal* signal = malloc(sizeof(DigitalSignal));
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signal->start_level = true;
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signal->edges_max_cnt = max_edges_cnt;
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2022-07-03 14:51:50 +00:00
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signal->edge_timings = malloc(max_edges_cnt * sizeof(uint32_t));
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2022-05-24 14:00:15 +00:00
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signal->reload_reg_buff = malloc(max_edges_cnt * sizeof(uint32_t));
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signal->edge_cnt = 0;
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return signal;
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}
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void digital_signal_free(DigitalSignal* signal) {
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furi_assert(signal);
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free(signal->edge_timings);
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free(signal->reload_reg_buff);
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free(signal);
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}
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bool digital_signal_append(DigitalSignal* signal_a, DigitalSignal* signal_b) {
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furi_assert(signal_a);
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furi_assert(signal_b);
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if(signal_a->edges_max_cnt < signal_a->edge_cnt + signal_b->edge_cnt) {
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return false;
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}
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bool end_level = signal_a->start_level;
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if(signal_a->edge_cnt) {
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end_level = signal_a->start_level ^ !(signal_a->edge_cnt % 2);
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}
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uint8_t start_copy = 0;
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if(end_level == signal_b->start_level) {
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if(signal_a->edge_cnt) {
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signal_a->edge_timings[signal_a->edge_cnt - 1] += signal_b->edge_timings[0];
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start_copy += 1;
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} else {
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signal_a->edge_timings[signal_a->edge_cnt] += signal_b->edge_timings[0];
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}
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}
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2022-07-03 14:51:50 +00:00
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for(size_t i = 0; i < signal_b->edge_cnt - start_copy; i++) {
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signal_a->edge_timings[signal_a->edge_cnt + i] = signal_b->edge_timings[start_copy + i];
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}
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2022-05-24 14:00:15 +00:00
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signal_a->edge_cnt += signal_b->edge_cnt - start_copy;
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return true;
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}
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bool digital_signal_get_start_level(DigitalSignal* signal) {
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furi_assert(signal);
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return signal->start_level;
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}
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uint32_t digital_signal_get_edges_cnt(DigitalSignal* signal) {
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furi_assert(signal);
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return signal->edge_cnt;
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}
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2022-07-03 14:51:50 +00:00
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uint32_t digital_signal_get_edge(DigitalSignal* signal, uint32_t edge_num) {
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2022-05-24 14:00:15 +00:00
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furi_assert(signal);
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furi_assert(edge_num < signal->edge_cnt);
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return signal->edge_timings[edge_num];
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}
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2022-07-03 14:51:50 +00:00
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void digital_signal_prepare_arr(DigitalSignal* signal) {
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uint32_t t_signal_rest = signal->edge_timings[0];
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uint32_t r_count_tick_arr = 0;
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uint32_t r_rest_div = 0;
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2022-05-24 14:00:15 +00:00
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for(size_t i = 0; i < signal->edge_cnt - 1; i++) {
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2022-07-03 14:51:50 +00:00
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r_count_tick_arr = t_signal_rest / T_TIM;
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r_rest_div = t_signal_rest % T_TIM;
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t_signal_rest = signal->edge_timings[i + 1] + r_rest_div;
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if(r_rest_div < T_TIM_DIV2) {
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signal->reload_reg_buff[i] = r_count_tick_arr - 1;
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} else {
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signal->reload_reg_buff[i] = r_count_tick_arr;
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t_signal_rest -= T_TIM;
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2022-05-24 14:00:15 +00:00
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}
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}
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}
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2022-07-03 14:51:50 +00:00
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void digital_signal_send(DigitalSignal* signal, const GpioPin* gpio) {
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furi_assert(signal);
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furi_assert(gpio);
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// Configure gpio as output
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furi_hal_gpio_init(gpio, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
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// Init gpio buffer and DMA channel
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uint16_t gpio_reg = gpio->port->ODR;
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uint16_t gpio_buff[2];
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if(signal->start_level) {
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gpio_buff[0] = gpio_reg | gpio->pin;
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gpio_buff[1] = gpio_reg & ~(gpio->pin);
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} else {
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gpio_buff[0] = gpio_reg & ~(gpio->pin);
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gpio_buff[1] = gpio_reg | gpio->pin;
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}
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LL_DMA_InitTypeDef dma_config = {};
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dma_config.MemoryOrM2MDstAddress = (uint32_t)gpio_buff;
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dma_config.PeriphOrM2MSrcAddress = (uint32_t) & (gpio->port->ODR);
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dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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dma_config.Mode = LL_DMA_MODE_CIRCULAR;
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dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
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dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
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dma_config.NbData = 2;
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dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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dma_config.Priority = LL_DMA_PRIORITY_VERYHIGH;
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LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
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LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, 2);
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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// Init timer arr register buffer and DMA channel
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digital_signal_prepare_arr(signal);
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dma_config.MemoryOrM2MDstAddress = (uint32_t)signal->reload_reg_buff;
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dma_config.PeriphOrM2MSrcAddress = (uint32_t) & (TIM2->ARR);
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dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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dma_config.Mode = LL_DMA_MODE_NORMAL;
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dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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dma_config.NbData = signal->edge_cnt - 2;
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dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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dma_config.Priority = LL_DMA_PRIORITY_HIGH;
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LL_DMA_Init(DMA1, LL_DMA_CHANNEL_2, &dma_config);
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LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_2, signal->edge_cnt - 2);
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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// Set up timer
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LL_TIM_SetCounterMode(TIM2, LL_TIM_COUNTERMODE_UP);
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LL_TIM_SetClockDivision(TIM2, LL_TIM_CLOCKDIVISION_DIV1);
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LL_TIM_SetPrescaler(TIM2, 0);
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LL_TIM_SetAutoReload(TIM2, 10);
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LL_TIM_SetCounter(TIM2, 0);
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LL_TIM_EnableUpdateEvent(TIM2);
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LL_TIM_EnableDMAReq_UPDATE(TIM2);
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// Start transactions
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LL_TIM_GenerateEvent_UPDATE(TIM2); // Do we really need it?
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LL_TIM_EnableCounter(TIM2);
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while(!LL_DMA_IsActiveFlag_TC2(DMA1))
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;
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LL_DMA_ClearFlag_TC1(DMA1);
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LL_DMA_ClearFlag_TC2(DMA1);
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LL_TIM_DisableCounter(TIM2);
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LL_TIM_SetCounter(TIM2, 0);
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
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}
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