2022-11-04 07:01:44 +00:00
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#include "magic.h"
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#include <furi_hal_nfc.h>
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#define TAG "Magic"
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#define MAGIC_CMD_WUPA (0x40)
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#define MAGIC_CMD_WIPE (0x41)
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2023-03-21 12:03:14 +00:00
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#define MAGIC_CMD_ACCESS (0x43)
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2022-11-04 07:01:44 +00:00
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#define MAGIC_MIFARE_READ_CMD (0x30)
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#define MAGIC_MIFARE_WRITE_CMD (0xA0)
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#define MAGIC_ACK (0x0A)
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#define MAGIC_BUFFER_SIZE (32)
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bool magic_wupa() {
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bool magic_activated = false;
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uint8_t tx_data[MAGIC_BUFFER_SIZE] = {};
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uint8_t rx_data[MAGIC_BUFFER_SIZE] = {};
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uint16_t rx_len = 0;
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FuriHalNfcReturn ret = 0;
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do {
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// Setup nfc poller
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furi_hal_nfc_exit_sleep();
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furi_hal_nfc_ll_txrx_on();
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furi_hal_nfc_ll_poll();
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ret = furi_hal_nfc_ll_set_mode(
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FuriHalNfcModePollNfca, FuriHalNfcBitrate106, FuriHalNfcBitrate106);
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if(ret != FuriHalNfcReturnOk) break;
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furi_hal_nfc_ll_set_fdt_listen(FURI_HAL_NFC_LL_FDT_LISTEN_NFCA_POLLER);
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furi_hal_nfc_ll_set_fdt_poll(FURI_HAL_NFC_LL_FDT_POLL_NFCA_POLLER);
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furi_hal_nfc_ll_set_error_handling(FuriHalNfcErrorHandlingNfc);
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furi_hal_nfc_ll_set_guard_time(FURI_HAL_NFC_LL_GT_NFCA);
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// Start communication
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tx_data[0] = MAGIC_CMD_WUPA;
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ret = furi_hal_nfc_ll_txrx_bits(
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tx_data,
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7,
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rx_data,
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sizeof(rx_data),
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&rx_len,
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FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_TX_MANUAL | FURI_HAL_NFC_LL_TXRX_FLAGS_AGC_ON |
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FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_RX_KEEP,
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furi_hal_nfc_ll_ms2fc(20));
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if(ret != FuriHalNfcReturnIncompleteByte) break;
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if(rx_len != 4) break;
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if(rx_data[0] != MAGIC_ACK) break;
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magic_activated = true;
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} while(false);
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if(!magic_activated) {
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furi_hal_nfc_ll_txrx_off();
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furi_hal_nfc_start_sleep();
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}
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return magic_activated;
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}
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bool magic_data_access_cmd() {
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bool write_cmd_success = false;
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uint8_t tx_data[MAGIC_BUFFER_SIZE] = {};
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uint8_t rx_data[MAGIC_BUFFER_SIZE] = {};
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uint16_t rx_len = 0;
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FuriHalNfcReturn ret = 0;
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do {
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2023-03-21 12:03:14 +00:00
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tx_data[0] = MAGIC_CMD_ACCESS;
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2022-11-04 07:01:44 +00:00
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ret = furi_hal_nfc_ll_txrx_bits(
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tx_data,
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8,
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rx_data,
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sizeof(rx_data),
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&rx_len,
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FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_TX_MANUAL | FURI_HAL_NFC_LL_TXRX_FLAGS_AGC_ON |
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FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_RX_KEEP,
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furi_hal_nfc_ll_ms2fc(20));
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if(ret != FuriHalNfcReturnIncompleteByte) break;
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if(rx_len != 4) break;
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if(rx_data[0] != MAGIC_ACK) break;
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write_cmd_success = true;
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} while(false);
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if(!write_cmd_success) {
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furi_hal_nfc_ll_txrx_off();
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furi_hal_nfc_start_sleep();
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}
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return write_cmd_success;
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}
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bool magic_read_block(uint8_t block_num, MfClassicBlock* data) {
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furi_assert(data);
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bool read_success = false;
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uint8_t tx_data[MAGIC_BUFFER_SIZE] = {};
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uint8_t rx_data[MAGIC_BUFFER_SIZE] = {};
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uint16_t rx_len = 0;
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FuriHalNfcReturn ret = 0;
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do {
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tx_data[0] = MAGIC_MIFARE_READ_CMD;
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tx_data[1] = block_num;
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ret = furi_hal_nfc_ll_txrx_bits(
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tx_data,
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2 * 8,
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rx_data,
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sizeof(rx_data),
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&rx_len,
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FURI_HAL_NFC_LL_TXRX_FLAGS_AGC_ON,
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furi_hal_nfc_ll_ms2fc(20));
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if(ret != FuriHalNfcReturnOk) break;
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if(rx_len != 16 * 8) break;
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memcpy(data->value, rx_data, sizeof(data->value));
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read_success = true;
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} while(false);
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if(!read_success) {
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furi_hal_nfc_ll_txrx_off();
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furi_hal_nfc_start_sleep();
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}
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return read_success;
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}
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bool magic_write_blk(uint8_t block_num, MfClassicBlock* data) {
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furi_assert(data);
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bool write_success = false;
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uint8_t tx_data[MAGIC_BUFFER_SIZE] = {};
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uint8_t rx_data[MAGIC_BUFFER_SIZE] = {};
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uint16_t rx_len = 0;
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FuriHalNfcReturn ret = 0;
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do {
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tx_data[0] = MAGIC_MIFARE_WRITE_CMD;
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tx_data[1] = block_num;
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ret = furi_hal_nfc_ll_txrx_bits(
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tx_data,
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2 * 8,
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rx_data,
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sizeof(rx_data),
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&rx_len,
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FURI_HAL_NFC_LL_TXRX_FLAGS_AGC_ON | FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_RX_KEEP,
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furi_hal_nfc_ll_ms2fc(20));
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if(ret != FuriHalNfcReturnIncompleteByte) break;
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if(rx_len != 4) break;
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if(rx_data[0] != MAGIC_ACK) break;
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memcpy(tx_data, data->value, sizeof(data->value));
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ret = furi_hal_nfc_ll_txrx_bits(
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tx_data,
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16 * 8,
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rx_data,
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sizeof(rx_data),
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&rx_len,
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FURI_HAL_NFC_LL_TXRX_FLAGS_AGC_ON | FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_RX_KEEP,
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furi_hal_nfc_ll_ms2fc(20));
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if(ret != FuriHalNfcReturnIncompleteByte) break;
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if(rx_len != 4) break;
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if(rx_data[0] != MAGIC_ACK) break;
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write_success = true;
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} while(false);
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if(!write_success) {
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furi_hal_nfc_ll_txrx_off();
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furi_hal_nfc_start_sleep();
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}
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return write_success;
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}
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bool magic_wipe() {
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bool wipe_success = false;
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uint8_t tx_data[MAGIC_BUFFER_SIZE] = {};
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uint8_t rx_data[MAGIC_BUFFER_SIZE] = {};
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uint16_t rx_len = 0;
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FuriHalNfcReturn ret = 0;
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do {
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tx_data[0] = MAGIC_CMD_WIPE;
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ret = furi_hal_nfc_ll_txrx_bits(
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tx_data,
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8,
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rx_data,
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sizeof(rx_data),
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&rx_len,
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FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_TX_MANUAL | FURI_HAL_NFC_LL_TXRX_FLAGS_AGC_ON |
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FURI_HAL_NFC_LL_TXRX_FLAGS_CRC_RX_KEEP,
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furi_hal_nfc_ll_ms2fc(2000));
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if(ret != FuriHalNfcReturnIncompleteByte) break;
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if(rx_len != 4) break;
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if(rx_data[0] != MAGIC_ACK) break;
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wipe_success = true;
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} while(false);
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return wipe_success;
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}
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void magic_deactivate() {
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furi_hal_nfc_ll_txrx_off();
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2022-11-10 16:29:57 +00:00
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furi_hal_nfc_sleep();
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2022-11-04 07:01:44 +00:00
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}
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