2021-09-10 02:19:02 +00:00
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/**
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2022-02-10 11:20:50 +00:00
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******************************************************************************
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* @file startup_stm32wb55xx_cm4.s
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* @author MCD Application Team
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* @brief STM32WB55xx devices vector table GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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2021-09-10 02:19:02 +00:00
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/* start address for the initialization values of the .data section.
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defined in linker script */
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2022-02-10 11:20:50 +00:00
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.word _sidata
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2021-09-10 02:19:02 +00:00
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/* start address for the .data section. defined in linker script */
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2022-02-10 11:20:50 +00:00
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.word _sdata
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2021-09-10 02:19:02 +00:00
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/* end address for the .data section. defined in linker script */
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2022-02-10 11:20:50 +00:00
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.word _edata
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2021-09-10 02:19:02 +00:00
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/* start address for the .bss section. defined in linker script */
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2022-02-10 11:20:50 +00:00
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.word _sbss
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2021-09-10 02:19:02 +00:00
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/* end address for the .bss section. defined in linker script */
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2022-02-10 11:20:50 +00:00
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.word _ebss
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2021-09-10 02:19:02 +00:00
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/* start address for the .MB_MEM2 section. defined in linker script */
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.word _sMB_MEM2
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/* end address for the .MB_MEM2 section. defined in linker script */
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.word _eMB_MEM2
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/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
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.macro INIT_BSS start, end
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2022-02-10 11:20:50 +00:00
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ldr r0, =\start
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ldr r1, =\end
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movs r3, #0
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bl LoopFillZerobss
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2021-09-10 02:19:02 +00:00
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.endm
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/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
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.macro INIT_DATA start, end, src
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2022-02-10 11:20:50 +00:00
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ldr r0, =\start
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ldr r1, =\end
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ldr r2, =\src
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movs r3, #0
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bl LoopCopyDataInit
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2021-09-10 02:19:02 +00:00
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.endm
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.section .text.data_initializers
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CopyDataInit:
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2022-02-10 11:20:50 +00:00
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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2021-09-10 02:19:02 +00:00
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LoopCopyDataInit:
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2022-02-10 11:20:50 +00:00
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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bx lr
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2021-09-10 02:19:02 +00:00
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FillZerobss:
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2022-02-10 11:20:50 +00:00
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str r3, [r0]
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adds r0, r0, #4
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2021-09-10 02:19:02 +00:00
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LoopFillZerobss:
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2022-02-10 11:20:50 +00:00
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cmp r0, r1
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bcc FillZerobss
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bx lr
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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2021-09-10 02:19:02 +00:00
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Reset_Handler:
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2022-02-10 11:20:50 +00:00
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Call the clock system intitialization function.*/
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bl SystemInit
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2021-09-10 02:19:02 +00:00
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/* Copy the data segment initializers from flash to SRAM */
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2022-02-10 11:20:50 +00:00
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INIT_DATA _sdata, _edata, _sidata
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2021-09-10 02:19:02 +00:00
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/* Zero fill the bss segments. */
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2022-02-10 11:20:50 +00:00
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INIT_BSS _sbss, _ebss
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INIT_BSS _sMB_MEM2, _eMB_MEM2
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2021-09-10 02:19:02 +00:00
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/* Call static constructors */
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2022-02-10 11:20:50 +00:00
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bl __libc_init_array
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2021-09-10 02:19:02 +00:00
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/* Call the application s entry point.*/
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2022-02-10 11:20:50 +00:00
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bl main
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2021-09-10 02:19:02 +00:00
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LoopForever:
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2022-02-10 11:20:50 +00:00
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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2021-09-10 02:19:02 +00:00
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval None
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*/
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2022-02-10 11:20:50 +00:00
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.section .text.Default_Handler,"ax",%progbits
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2021-09-10 02:19:02 +00:00
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Default_Handler:
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Infinite_Loop:
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2022-02-10 11:20:50 +00:00
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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2021-09-10 02:19:02 +00:00
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/******************************************************************************
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*
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* The minimal vector table for a Cortex-M4. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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2022-02-10 11:20:50 +00:00
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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2021-09-10 02:19:02 +00:00
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g_pfnVectors:
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2022-02-10 11:20:50 +00:00
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler
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.word PVD_PVM_IRQHandler
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.word TAMP_STAMP_LSECSS_IRQHandler
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.word RTC_WKUP_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_IRQHandler
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.word DMA1_Channel3_IRQHandler
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.word DMA1_Channel4_IRQHandler
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.word DMA1_Channel5_IRQHandler
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word ADC1_IRQHandler
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.word USB_HP_IRQHandler
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.word USB_LP_IRQHandler
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.word C2SEV_PWR_C2H_IRQHandler
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.word COMP_IRQHandler
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.word EXTI9_5_IRQHandler
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.word TIM1_BRK_IRQHandler
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.word TIM1_UP_TIM16_IRQHandler
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.word TIM1_TRG_COM_TIM17_IRQHandler
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.word TIM1_CC_IRQHandler
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.word TIM2_IRQHandler
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.word PKA_IRQHandler
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.word I2C1_EV_IRQHandler
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.word I2C1_ER_IRQHandler
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.word I2C3_EV_IRQHandler
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.word I2C3_ER_IRQHandler
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.word SPI1_IRQHandler
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.word SPI2_IRQHandler
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.word USART1_IRQHandler
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.word LPUART1_IRQHandler
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.word SAI1_IRQHandler
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.word TSC_IRQHandler
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.word EXTI15_10_IRQHandler
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.word RTC_Alarm_IRQHandler
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.word CRS_IRQHandler
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.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
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.word IPCC_C1_RX_IRQHandler
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.word IPCC_C1_TX_IRQHandler
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.word HSEM_IRQHandler
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.word LPTIM1_IRQHandler
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.word LPTIM2_IRQHandler
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.word LCD_IRQHandler
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.word QUADSPI_IRQHandler
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.word AES1_IRQHandler
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.word AES2_IRQHandler
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.word RNG_IRQHandler
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.word FPU_IRQHandler
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.word DMA2_Channel1_IRQHandler
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.word DMA2_Channel2_IRQHandler
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.word DMA2_Channel3_IRQHandler
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.word DMA2_Channel4_IRQHandler
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.word DMA2_Channel5_IRQHandler
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.word DMA2_Channel6_IRQHandler
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.word DMA2_Channel7_IRQHandler
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.word DMAMUX1_OVR_IRQHandler
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2021-09-10 02:19:02 +00:00
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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2022-02-10 11:20:50 +00:00
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak MemManage_Handler
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.thumb_set MemManage_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak BusFault_Handler
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.thumb_set BusFault_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak PVD_PVM_IRQHandler
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.thumb_set PVD_PVM_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TAMP_STAMP_LSECSS_IRQHandler
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.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak RTC_WKUP_IRQHandler
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel1_IRQHandler
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.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel2_IRQHandler
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.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel3_IRQHandler
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.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel4_IRQHandler
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.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel5_IRQHandler
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.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel6_IRQHandler
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.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA1_Channel7_IRQHandler
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.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak ADC1_IRQHandler
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.thumb_set ADC1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak USB_HP_IRQHandler
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.thumb_set USB_HP_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak USB_LP_IRQHandler
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.thumb_set USB_LP_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak C2SEV_PWR_C2H_IRQHandler
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.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak COMP_IRQHandler
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.thumb_set COMP_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI9_5_IRQHandler
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.thumb_set EXTI9_5_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TIM1_BRK_IRQHandler
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.thumb_set TIM1_BRK_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TIM1_UP_TIM16_IRQHandler
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.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TIM1_TRG_COM_TIM17_IRQHandler
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.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak PKA_IRQHandler
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.thumb_set PKA_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak I2C1_EV_IRQHandler
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.thumb_set I2C1_EV_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak I2C1_ER_IRQHandler
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.thumb_set I2C1_ER_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak I2C3_EV_IRQHandler
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.thumb_set I2C3_EV_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak I2C3_ER_IRQHandler
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.thumb_set I2C3_ER_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak SPI2_IRQHandler
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.thumb_set SPI2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak LPUART1_IRQHandler
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.thumb_set LPUART1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak SAI1_IRQHandler
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.thumb_set SAI1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak TSC_IRQHandler
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.thumb_set TSC_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak EXTI15_10_IRQHandler
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.thumb_set EXTI15_10_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak RTC_Alarm_IRQHandler
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.thumb_set RTC_Alarm_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak CRS_IRQHandler
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.thumb_set CRS_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
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.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak IPCC_C1_RX_IRQHandler
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.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak IPCC_C1_TX_IRQHandler
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.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak HSEM_IRQHandler
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.thumb_set HSEM_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak LPTIM1_IRQHandler
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.thumb_set LPTIM1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak LPTIM2_IRQHandler
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.thumb_set LPTIM2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak LCD_IRQHandler
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.thumb_set LCD_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak QUADSPI_IRQHandler
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.thumb_set QUADSPI_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak AES1_IRQHandler
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.thumb_set AES1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak AES2_IRQHandler
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.thumb_set AES2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak RNG_IRQHandler
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.thumb_set RNG_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak FPU_IRQHandler
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.thumb_set FPU_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel1_IRQHandler
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.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel2_IRQHandler
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.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel3_IRQHandler
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.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel4_IRQHandler
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.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel5_IRQHandler
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.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel6_IRQHandler
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.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMA2_Channel7_IRQHandler
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.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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2022-02-10 11:20:50 +00:00
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.weak DMAMUX1_OVR_IRQHandler
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.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
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2021-09-10 02:19:02 +00:00
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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