Skorp subghz signal archive (#667)

* SubGhz: Add millis() furi, add subghz history struct
* SubGhz: Fix subghz history
* Gubghz: Fix code repeat  history, add clean history
* SubGhz: reading and adding keys to history
* Gui: Renaming Sub 1-Ghz -> SubGhz
* Archive: Renaming Sub 1-Ghz -> SubGhz
* SubGhz:  Add menu history, modified button for sending a signal, changed output of data about accepted protocol
* Archive: Fix name subghz
* SubGhz: Menu navigation
* Assets: Add assets/SubGHz/icon.png
* Assets: add new icons for subghz
* SubGhz: Fix name Add manually scene
* SubGhz: Fix load icon Read scene. rename encoder struct,  rename protocol function load from file, add load raw data protocol, add info pleasant signals all protocol
* SubGhz: fix memory leak
* SubGhz: change of receiving frequency for read scene
* SubGhz: Add save/load frequency and preset, add automatic configuration of transmit/receive to the desired frequency and modulation, add button "save" config scene
* SubGhz: Fix frequency and preset, fix frequency add manualli scene, fix re-executing the parser
* Furi-hal-subghz: add 2-FSK config, fix ook config 650KHz BW Tx filter
* Fix formatting and release build
* SubGhz: Delete read scene
* SubGhz: Fix frequency add manualli scene,  refactoring code
* SubGhz: 2 profiles for OOK, fix broken build.
* SubGhz: Add passing static codes from read scene, add notification read scene, refactoring code
* SubGhz: fix assert on worker double stop.

Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
This commit is contained in:
Skorpionm
2021-08-28 17:51:48 +04:00
committed by GitHub
parent c3a1836fcd
commit 0a8a944e10
64 changed files with 1563 additions and 402 deletions

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@@ -28,3 +28,7 @@ void delay(float milliseconds) {
(void)result;
furi_assert(result == osOK);
}
uint32_t millis(void){
return HAL_GetTick();
}

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@@ -411,7 +411,9 @@ static void furi_hal_irda_tx_fill_buffer_last(uint8_t buf_num) {
furi_assert(irda_tim_tx.data_callback);
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
furi_assert(buffer->data != NULL);
(void)buffer->data;
furi_assert(buffer->polarity != NULL);
(void)buffer->polarity;
irda_tim_tx.buffer[buf_num].data[0] = 0; // 1 pulse
irda_tim_tx.buffer[buf_num].polarity[0] = IRDA_TX_CCMR_LOW;

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@@ -11,14 +11,14 @@
static volatile SubGhzState furi_hal_subghz_state = SubGhzStateInit;
static const uint8_t furi_hal_subghz_preset_ook_async_regs[][2] = {
static const uint8_t furi_hal_subghz_preset_ook_270khz_async_regs[][2] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{ CC1101_IOCFG0, 0x0D }, // GD0 as async serial data output/input
/* FIFO and internals */
{ CC1101_FIFOTHR, 0x47 }, // The only important bit is ADC_RETENTION
{ CC1101_FIFOTHR, 0x47 }, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
/* Packet engine */
{ CC1101_PKTCTRL0, 0x32 }, // Async, continious, no whitening
@@ -66,6 +66,116 @@ static const uint8_t furi_hal_subghz_preset_ook_async_regs[][2] = {
{ 0, 0 },
};
static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{ CC1101_IOCFG0, 0x0D }, // GD0 as async serial data output/input
/* FIFO and internals */
{ CC1101_FIFOTHR, 0x07 }, // The only important bit is ADC_RETENTION
/* Packet engine */
{ CC1101_PKTCTRL0, 0x32 }, // Async, continious, no whitening
/* Frequency Synthesizer Control */
{ CC1101_FSCTRL1, 0x06 }, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
{ CC1101_MDMCFG0, 0x00 }, // Channel spacing is 25kHz
{ CC1101_MDMCFG1, 0x00 }, // Channel spacing is 25kHz
{ CC1101_MDMCFG2, 0x30 }, // Format ASK/OOK, No preamble/sync
{ CC1101_MDMCFG3, 0x32 }, // Data rate is 3.79372 kBaud
{ CC1101_MDMCFG4, 0x17 }, // Rx BW filter is 650.000kHz
/* Main Radio Control State Machine */
{ CC1101_MCSM0, 0x18 }, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{ CC1101_FOCCFG, 0x18 }, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{ CC1101_AGCTRL0, 0x40 }, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
{ CC1101_AGCTRL1, 0x00 }, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{ CC1101_AGCTRL2, 0x03 }, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
/* Wake on radio and timeouts control */
{ CC1101_WORCTRL, 0xFB }, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{ CC1101_FREND0, 0x11 }, // Adjusts current TX LO buffer + high is PATABLE[1]
{ CC1101_FREND1, 0xB6 }, //
/* Frequency Synthesizer Calibration, valid for 433.92 */
{ CC1101_FSCAL3, 0xE9 },
{ CC1101_FSCAL2, 0x2A },
{ CC1101_FSCAL1, 0x00 },
{ CC1101_FSCAL0, 0x1F },
/* Magic f4ckery */
{ CC1101_TEST2, 0x88 },
{ CC1101_TEST1, 0x31 },
{ CC1101_TEST0, 0x09 }, // VCO selection calibration stage is disabled
/* End */
{ 0, 0 },
};
static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
/* GPIO GD0 */
{ CC1101_IOCFG0, 0x0D }, // GD0 as async serial data output/input
/* FIFO and internals */
{ CC1101_FIFOTHR, 0x47 }, // The only important bit is ADC_RETENTION
/* Packet engine */
{ CC1101_PKTCTRL0, 0x32 }, // Async, continious, no whitening
/* Frequency Synthesizer Control */
{ CC1101_FSCTRL1, 0x06 }, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
// Modem Configuration
{ CC1101_MDMCFG0, 0xF8 },
{ CC1101_MDMCFG1, 0x00 }, // No preamble/sync
{ CC1101_MDMCFG2, 0x80 }, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
{ CC1101_MDMCFG3, 0x83 }, // Data rate is 9.59587 kBaud
{ CC1101_MDMCFG4, 0x88 }, // Rx BW filter is 203.125000kHz
{ CC1101_DEVIATN, 0x14}, //Deviation 4.760742 khz
/* Main Radio Control State Machine */
{ CC1101_MCSM0, 0x18 }, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
/* Frequency Offset Compensation Configuration */
{ CC1101_FOCCFG, 0x18 }, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
/* Automatic Gain Control */
{ CC1101_AGCTRL0, 0x40 }, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
{ CC1101_AGCTRL1, 0x00 }, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
{ CC1101_AGCTRL2, 0x03 }, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
/* Wake on radio and timeouts control */
{ CC1101_WORCTRL, 0xFB }, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
/* Frontend configuration */
{ CC1101_FREND0, 0x10 }, // Adjusts current TX LO buffer
{ CC1101_FREND1, 0xB6 }, //
/* Frequency Synthesizer Calibration, valid for 433.92 */
{ CC1101_FSCAL3, 0xE9 },
{ CC1101_FSCAL2, 0x2A },
{ CC1101_FSCAL1, 0x00 },
{ CC1101_FSCAL0, 0x1F },
/* Magic f4ckery */
{ CC1101_TEST2, 0x81 }, // FIFOTHR ADC_RETENTION=1 matched value
{ CC1101_TEST1, 0x35 }, // FIFOTHR ADC_RETENTION=1 matched value
{ CC1101_TEST0, 0x09 }, // VCO selection calibration stage is disabled
/* End */
{ 0, 0 },
};
static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
0x00,
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
@@ -76,6 +186,16 @@ static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
0x00,
0x00
};
static const uint8_t furi_hal_subghz_preset_2fsk_async_patable[8] = {
0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
void furi_hal_subghz_init() {
furi_assert(furi_hal_subghz_state == SubGhzStateInit);
@@ -143,10 +263,16 @@ void furi_hal_subghz_dump_state() {
}
void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
if(preset == FuriHalSubGhzPresetOokAsync) {
furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_async_regs);
if(preset == FuriHalSubGhzPresetOok650Async) {
furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_650khz_async_regs);
furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
} else {
} else if(preset == FuriHalSubGhzPresetOok270Async){
furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_270khz_async_regs);
furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
} else if(preset == FuriHalSubGhzPreset2FSKAsync){
furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_async_regs);
furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
}else {
furi_check(0);
}
}

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@@ -17,6 +17,9 @@ void delay(float milliseconds);
/** Delay in microseconds */
void delay_us(float microseconds);
/** Get current millisecond */
uint32_t millis(void);
#ifdef __cplusplus
}
#endif

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@@ -11,7 +11,9 @@ extern "C" {
/** Radio Presets */
typedef enum {
FuriHalSubGhzPresetOokAsync, /** OOK, asynchronous */
FuriHalSubGhzPresetOok270Async, /** OOK, bandwidth 270kHz, asynchronous */
FuriHalSubGhzPresetOok650Async, /** OOK, bandwidth 650kHz, asynchronous */
FuriHalSubGhzPreset2FSKAsync, /** FM, asynchronous */
} FuriHalSubGhzPreset;
/** Switchable Radio Paths */