[FL-1610] SubGhz: scene based application, PT save and replay (#630)
* SubGhz: scene based application * SubGhz: encoder/decoder separation, DMA streaming, update app and cli. * SubGhz: 2 stage async tx complete, minor cleanup * SubGhz: 2 stage async tx complete, FIX state pin end transmit * SubGhz: Pricenton, receive TE signal * SubGhz: Pricenton, add save data, add load data * SubGhz: Add Read scene, Fix pricenton save, load funtion * SubGhz: Add Read, Receiver, SaveName scene * SubGhz: Read and Save (pricenton) * SubGhz: add Load scence * SubGhz: Fix select file scene, add load scene, add transmitter view, add send tx pricenton * SubGhz: Fix pricenton encoder, fix transmitter send * SubGhz: modified Pricenton Encoder (added guard time at the beginning), modified CC1101 config, code refactoring * SubGhz: Fix pricenton encoder defalut TE * Archive: Fix path and name SubGhz * Archive: Fix name app SubGhz * GubGhz: Came: add Save, Load key * GubGhz: GateTX: add Save, Load key * GubGhz: NeroSketch: add Save, Load key * Github: better linters triggers * SubGhz: adding fast loading keys Archive -> Run in app * GubGhz: KeeLog: add Save, Load key, key generation from the serial number of the meter and the button * SubGhz: format sources and fix compilation * FuriHal: add subghz configuration description for AGC section * SubGhz: save only protocols that can be saved. Cleanup. * Github: lint on pull requests Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
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@@ -40,8 +40,9 @@ static const uint8_t furi_hal_subghz_preset_ook_async_regs[][2] = {
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{ CC1101_FOCCFG, 0x18 }, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{ CC1101_AGCTRL1, 0x00 }, // LNA 2 gain is decreased to minimum before decreasing LNA gain
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{ CC1101_AGCTRL2, 0x07 }, // MAGN_TARGET is 42 dB
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{ CC1101_AGCTRL0, 0x40 }, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{ CC1101_AGCTRL1, 0x00 }, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{ CC1101_AGCTRL2, 0x03 }, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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{ CC1101_WORCTRL, 0xFB }, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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@@ -323,15 +324,14 @@ static void furi_hal_subghz_capture_ISR() {
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}
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}
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void furi_hal_subghz_set_async_rx_callback(FuriHalSubGhzCaptureCallback callback, void* context) {
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furi_hal_subghz_capture_callback = callback;
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furi_hal_subghz_capture_callback_context = context;
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}
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void furi_hal_subghz_start_async_rx() {
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void furi_hal_subghz_start_async_rx(FuriHalSubGhzCaptureCallback callback, void* context) {
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furi_assert(furi_hal_subghz_state == SubGhzStateIdle);
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furi_hal_subghz_state = SubGhzStateAsyncRx;
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furi_hal_subghz_capture_callback = callback;
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furi_hal_subghz_capture_callback_context = context;
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hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullNo, GpioSpeedLow, GpioAltFn1TIM2);
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// Timer: base
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@@ -402,33 +402,73 @@ void furi_hal_subghz_stop_async_rx() {
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hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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}
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volatile size_t furi_hal_subghz_tx_repeat = 0;
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#define API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL (256)
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#define API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF (API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL/2)
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static void furi_hal_subghz_tx_dma_isr() {
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typedef struct {
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uint32_t* buffer;
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bool flip_flop;
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FuriHalSubGhzAsyncTxCallback callback;
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void* callback_context;
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} FuriHalSubGhzAsyncTx;
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static FuriHalSubGhzAsyncTx furi_hal_subghz_async_tx = {0};
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static void furi_hal_subghz_async_tx_refill(uint32_t* buffer, size_t samples) {
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while (samples > 0) {
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LevelDuration ld = furi_hal_subghz_async_tx.callback(furi_hal_subghz_async_tx.callback_context);
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if (level_duration_is_reset(ld)) {
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break;
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} else {
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uint32_t duration = level_duration_get_duration(ld);
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assert(duration > 0);
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*buffer = duration;
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}
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buffer++;
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samples--;
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}
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memset(buffer, 0, samples * sizeof(uint32_t));
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}
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static void furi_hal_subghz_async_tx_dma_isr() {
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furi_assert(furi_hal_subghz_state == SubGhzStateAsyncTx);
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if (LL_DMA_IsActiveFlag_HT1(DMA1)) {
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LL_DMA_ClearFlag_HT1(DMA1);
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furi_hal_subghz_async_tx_refill(furi_hal_subghz_async_tx.buffer, API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF);
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}
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if (LL_DMA_IsActiveFlag_TC1(DMA1)) {
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LL_DMA_ClearFlag_TC1(DMA1);
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furi_assert(furi_hal_subghz_state == SubGhzStateAsyncTx);
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if (--furi_hal_subghz_tx_repeat == 0) {
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furi_hal_subghz_state = SubGhzStateAsyncTxLast;
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
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}
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furi_hal_subghz_async_tx_refill(furi_hal_subghz_async_tx.buffer+API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF, API_HAL_SUBGHZ_ASYNC_TX_BUFFER_HALF);
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}
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}
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static void furi_hal_subghz_tx_timer_isr() {
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static void furi_hal_subghz_async_tx_timer_isr() {
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if(LL_TIM_IsActiveFlag_UPDATE(TIM2)) {
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LL_TIM_ClearFlag_UPDATE(TIM2);
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if (furi_hal_subghz_state == SubGhzStateAsyncTxLast) {
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LL_TIM_DisableCounter(TIM2);
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furi_hal_subghz_state = SubGhzStateAsyncTxEnd;
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if (LL_TIM_GetAutoReload(TIM2) == 0) {
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if (furi_hal_subghz_state == SubGhzStateAsyncTx) {
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furi_hal_subghz_state = SubGhzStateAsyncTxLast;
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} else {
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furi_hal_subghz_state = SubGhzStateAsyncTxEnd;
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LL_TIM_DisableCounter(TIM2);
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hal_gpio_init(&gpio_cc1101_g0, GpioModeOutputPushPull, GpioPullDown, GpioSpeedLow);
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}
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}
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}
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}
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void furi_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t repeat) {
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void furi_hal_subghz_start_async_tx(FuriHalSubGhzAsyncTxCallback callback, void* context) {
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furi_assert(furi_hal_subghz_state == SubGhzStateIdle);
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furi_assert(callback);
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furi_hal_subghz_async_tx.callback = callback;
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furi_hal_subghz_async_tx.callback_context = context;
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furi_hal_subghz_state = SubGhzStateAsyncTx;
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furi_hal_subghz_tx_repeat = repeat;
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furi_hal_subghz_async_tx.buffer = furi_alloc(API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL * sizeof(uint32_t));
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furi_hal_subghz_async_tx_refill(furi_hal_subghz_async_tx.buffer, API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL);
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// Connect CC1101_GD0 to TIM2 as output
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hal_gpio_init_ex(&gpio_cc1101_g0, GpioModeAltFunctionPushPull, GpioPullDown, GpioSpeedLow, GpioAltFn1TIM2);
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@@ -436,19 +476,20 @@ void furi_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t
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// Configure DMA
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LL_DMA_InitTypeDef dma_config = {0};
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dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM2->ARR);
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dma_config.MemoryOrM2MDstAddress = (uint32_t)buffer;
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dma_config.MemoryOrM2MDstAddress = (uint32_t)furi_hal_subghz_async_tx.buffer;
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dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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dma_config.Mode = LL_DMA_MODE_CIRCULAR;
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dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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dma_config.NbData = buffer_size / sizeof(uint32_t);
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dma_config.NbData = API_HAL_SUBGHZ_ASYNC_TX_BUFFER_FULL;
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dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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dma_config.Priority = LL_DMA_MODE_NORMAL;
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LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
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furi_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, furi_hal_subghz_tx_dma_isr);
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furi_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, furi_hal_subghz_async_tx_dma_isr);
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LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
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LL_DMA_EnableIT_HT(DMA1, LL_DMA_CHANNEL_1);
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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// Configure TIM2
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@@ -473,7 +514,7 @@ void furi_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t
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LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH2);
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LL_TIM_DisableMasterSlaveMode(TIM2);
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furi_hal_interrupt_set_timer_isr(TIM2, furi_hal_subghz_tx_timer_isr);
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furi_hal_interrupt_set_timer_isr(TIM2, furi_hal_subghz_async_tx_timer_isr);
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LL_TIM_EnableIT_UPDATE(TIM2);
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LL_TIM_EnableDMAReq_UPDATE(TIM2);
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LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
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@@ -493,12 +534,8 @@ void furi_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t
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LL_TIM_EnableCounter(TIM2);
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}
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size_t furi_hal_subghz_get_async_tx_repeat_left() {
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return furi_hal_subghz_tx_repeat;
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}
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void furi_hal_subghz_wait_async_tx() {
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while(furi_hal_subghz_state != SubGhzStateAsyncTxEnd) osDelay(1);
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bool furi_hal_subghz_is_async_tx_complete() {
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return furi_hal_subghz_state == SubGhzStateAsyncTxEnd;
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}
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void furi_hal_subghz_stop_async_tx() {
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@@ -526,5 +563,7 @@ void furi_hal_subghz_stop_async_tx() {
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// Deinitialize GPIO
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hal_gpio_init(&gpio_cc1101_g0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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free(furi_hal_subghz_async_tx.buffer);
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furi_hal_subghz_state = SubGhzStateIdle;
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}
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@@ -132,35 +132,29 @@ void furi_hal_subghz_set_path(FuriHalSubGhzPath path);
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/** Signal Timings Capture callback */
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typedef void (*FuriHalSubGhzCaptureCallback)(bool level, uint32_t duration, void* context);
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/** Set signal timings capture callback
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* @param callback - your callback for front capture
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*/
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void furi_hal_subghz_set_async_rx_callback(FuriHalSubGhzCaptureCallback callback, void* context);
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/** Enable signal timings capture
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* Initializes GPIO and TIM2 for timings capture
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*/
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void furi_hal_subghz_start_async_rx();
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void furi_hal_subghz_start_async_rx(FuriHalSubGhzCaptureCallback callback, void* context);
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/** Disable signal timings capture
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* Resets GPIO and TIM2
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*/
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void furi_hal_subghz_stop_async_rx();
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/** Send buffer
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* Initializes GPIO, TIM2 and DMA1 for signal output
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* @param buffer - pointer to data buffer
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* @param buffer_size - buffer size in bytes
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/** Async TX callback type
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* @param context - callback context
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* @return LevelDuration
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*/
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void furi_hal_subghz_start_async_tx(uint32_t* buffer, size_t buffer_size, size_t repeat);
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typedef LevelDuration (*FuriHalSubGhzAsyncTxCallback)(void* context);
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/** Get repeats left count for async tx
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* @return packets left to send
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/** Start async TX
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* Initializes GPIO, TIM2 and DMA1 for signal output
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*/
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size_t furi_hal_subghz_get_async_tx_repeat_left();
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void furi_hal_subghz_start_async_tx(FuriHalSubGhzAsyncTxCallback callback, void* context);
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/** Wait for async transmission to complete */
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void furi_hal_subghz_wait_async_tx();
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bool furi_hal_subghz_is_async_tx_complete();
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/** Stop async transmission and cleanup resources
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* Resets GPIO, TIM2, and DMA1
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