diff --git a/firmware/targets/f3/Inc/stm32wbxx_hal_conf.h b/firmware/targets/f3/Inc/stm32wbxx_hal_conf.h
index 57e2d7cb..a0789d2f 100644
--- a/firmware/targets/f3/Inc/stm32wbxx_hal_conf.h
+++ b/firmware/targets/f3/Inc/stm32wbxx_hal_conf.h
@@ -152,7 +152,7 @@
 #endif /* HSI48_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
-#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#define LSE_STARTUP_TIMEOUT    1000U      /*!< Time out for LSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
diff --git a/firmware/targets/f3/Inc/stm32wbxx_it.h b/firmware/targets/f3/Inc/stm32wbxx_it.h
index d5351b83..c76192d9 100644
--- a/firmware/targets/f3/Inc/stm32wbxx_it.h
+++ b/firmware/targets/f3/Inc/stm32wbxx_it.h
@@ -53,6 +53,8 @@ void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
+void TAMP_STAMP_LSECSS_IRQHandler(void);
+void RCC_IRQHandler(void);
 void EXTI1_IRQHandler(void);
 void EXTI2_IRQHandler(void);
 void ADC1_IRQHandler(void);
diff --git a/firmware/targets/f3/Src/main.c b/firmware/targets/f3/Src/main.c
index b54b01bb..3e57fcd5 100644
--- a/firmware/targets/f3/Src/main.c
+++ b/firmware/targets/f3/Src/main.c
@@ -154,7 +154,7 @@ void SystemClock_Config(void)
   /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);
   /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@@ -220,7 +220,11 @@ void SystemClock_Config(void)
     Error_Handler();
   }
   /* USER CODE BEGIN Smps */
-
+  if (!LL_RCC_LSE_IsReady()) {
+    LL_RCC_ForceBackupDomainReset();
+    LL_RCC_ReleaseBackupDomainReset();
+    NVIC_SystemReset();
+  }
   /* USER CODE END Smps */
   /** Enables the Clock Security System
   */
diff --git a/firmware/targets/f3/Src/rtc.c b/firmware/targets/f3/Src/rtc.c
index 636877d2..a09cd28b 100644
--- a/firmware/targets/f3/Src/rtc.c
+++ b/firmware/targets/f3/Src/rtc.c
@@ -86,6 +86,10 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
     /* RTC clock enable */
     __HAL_RCC_RTC_ENABLE();
     __HAL_RCC_RTCAPB_CLK_ENABLE();
+
+    /* RTC interrupt Init */
+    HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
   /* USER CODE BEGIN RTC_MspInit 1 */
 
   /* USER CODE END RTC_MspInit 1 */
@@ -103,6 +107,9 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
     __HAL_RCC_RTCAPB_CLK_DISABLE();
+
+    /* RTC interrupt Deinit */
+    HAL_NVIC_DisableIRQ(TAMP_STAMP_LSECSS_IRQn);
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/firmware/targets/f3/Src/stm32wbxx_hal_msp.c b/firmware/targets/f3/Src/stm32wbxx_hal_msp.c
index 4b2a90aa..c96a5dfa 100644
--- a/firmware/targets/f3/Src/stm32wbxx_hal_msp.c
+++ b/firmware/targets/f3/Src/stm32wbxx_hal_msp.c
@@ -74,6 +74,9 @@ void HAL_MspInit(void)
   HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 
   /* Peripheral interrupt init */
+  /* RCC_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(RCC_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(RCC_IRQn);
   /* HSEM_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(HSEM_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(HSEM_IRQn);
diff --git a/firmware/targets/f3/Src/stm32wbxx_it.c b/firmware/targets/f3/Src/stm32wbxx_it.c
index 29c30393..e019e834 100644
--- a/firmware/targets/f3/Src/stm32wbxx_it.c
+++ b/firmware/targets/f3/Src/stm32wbxx_it.c
@@ -59,6 +59,7 @@
 extern PCD_HandleTypeDef hpcd_USB_FS;
 extern ADC_HandleTypeDef hadc1;
 extern COMP_HandleTypeDef hcomp1;
+extern RTC_HandleTypeDef hrtc;
 extern TIM_HandleTypeDef htim1;
 extern TIM_HandleTypeDef htim2;
 extern TIM_HandleTypeDef htim17;
@@ -166,6 +167,34 @@ void DebugMon_Handler(void)
 /* please refer to the startup file (startup_stm32wbxx.s).                    */
 /******************************************************************************/
 
+/**
+  * @brief This function handles RTC tamper and time stamp, CSS on LSE interrupts through EXTI line 18.
+  */
+void TAMP_STAMP_LSECSS_IRQHandler(void)
+{
+  /* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 0 */
+  HAL_RCC_CSSCallback();
+  /* USER CODE END TAMP_STAMP_LSECSS_IRQn 0 */
+  /* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 1 */
+
+  /* USER CODE END TAMP_STAMP_LSECSS_IRQn 1 */
+}
+
+/**
+  * @brief This function handles RCC global interrupt.
+  */
+void RCC_IRQHandler(void)
+{
+  /* USER CODE BEGIN RCC_IRQn 0 */
+  if (!LL_RCC_LSE_IsReady()) {
+    HAL_RCC_CSSCallback();
+  }
+  /* USER CODE END RCC_IRQn 0 */
+  /* USER CODE BEGIN RCC_IRQn 1 */
+
+  /* USER CODE END RCC_IRQn 1 */
+}
+
 /**
   * @brief This function handles EXTI line1 interrupt.
   */
diff --git a/firmware/targets/f3/api-hal/api-hal-power.c b/firmware/targets/f3/api-hal/api-hal-power.c
index 5257dbfc..abe79e1c 100644
--- a/firmware/targets/f3/api-hal/api-hal-power.c
+++ b/firmware/targets/f3/api-hal/api-hal-power.c
@@ -1,7 +1,14 @@
 #include <api-hal-power.h>
+#include <main.h>
 #include <bq27220.h>
 #include <bq25896.h>
 
+void HAL_RCC_CSSCallback(void) {
+    LL_RCC_ForceBackupDomainReset();
+    LL_RCC_ReleaseBackupDomainReset();
+    NVIC_SystemReset();
+}
+
 void api_hal_power_init() {
     bq27220_init();
     bq25896_init();
diff --git a/firmware/targets/f3/f3-1/Inc/stm32wbxx_hal_conf.h b/firmware/targets/f3/f3-1/Inc/stm32wbxx_hal_conf.h
index 57e2d7cb..a0789d2f 100644
--- a/firmware/targets/f3/f3-1/Inc/stm32wbxx_hal_conf.h
+++ b/firmware/targets/f3/f3-1/Inc/stm32wbxx_hal_conf.h
@@ -152,7 +152,7 @@
 #endif /* HSI48_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
-#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#define LSE_STARTUP_TIMEOUT    1000U      /*!< Time out for LSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
diff --git a/firmware/targets/f3/f3-1/Inc/stm32wbxx_it.h b/firmware/targets/f3/f3-1/Inc/stm32wbxx_it.h
index 59864278..3d30f4d8 100644
--- a/firmware/targets/f3/f3-1/Inc/stm32wbxx_it.h
+++ b/firmware/targets/f3/f3-1/Inc/stm32wbxx_it.h
@@ -53,6 +53,8 @@ void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
+void TAMP_STAMP_LSECSS_IRQHandler(void);
+void RCC_IRQHandler(void);
 void EXTI1_IRQHandler(void);
 void EXTI3_IRQHandler(void);
 void ADC1_IRQHandler(void);
diff --git a/firmware/targets/f3/f3-1/Src/main.c b/firmware/targets/f3/f3-1/Src/main.c
index b54b01bb..b67b2d56 100644
--- a/firmware/targets/f3/f3-1/Src/main.c
+++ b/firmware/targets/f3/f3-1/Src/main.c
@@ -154,7 +154,7 @@ void SystemClock_Config(void)
   /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);
   /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
@@ -221,6 +221,12 @@ void SystemClock_Config(void)
   }
   /* USER CODE BEGIN Smps */
 
+  if (!LL_RCC_LSE_IsReady()) {
+    LL_RCC_ForceBackupDomainReset();
+    LL_RCC_ReleaseBackupDomainReset();
+    NVIC_SystemReset();
+  }
+
   /* USER CODE END Smps */
   /** Enables the Clock Security System
   */
diff --git a/firmware/targets/f3/f3-1/Src/rtc.c b/firmware/targets/f3/f3-1/Src/rtc.c
index 636877d2..a09cd28b 100644
--- a/firmware/targets/f3/f3-1/Src/rtc.c
+++ b/firmware/targets/f3/f3-1/Src/rtc.c
@@ -86,6 +86,10 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
     /* RTC clock enable */
     __HAL_RCC_RTC_ENABLE();
     __HAL_RCC_RTCAPB_CLK_ENABLE();
+
+    /* RTC interrupt Init */
+    HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
   /* USER CODE BEGIN RTC_MspInit 1 */
 
   /* USER CODE END RTC_MspInit 1 */
@@ -103,6 +107,9 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
     /* Peripheral clock disable */
     __HAL_RCC_RTC_DISABLE();
     __HAL_RCC_RTCAPB_CLK_DISABLE();
+
+    /* RTC interrupt Deinit */
+    HAL_NVIC_DisableIRQ(TAMP_STAMP_LSECSS_IRQn);
   /* USER CODE BEGIN RTC_MspDeInit 1 */
 
   /* USER CODE END RTC_MspDeInit 1 */
diff --git a/firmware/targets/f3/f3-1/Src/stm32wbxx_hal_msp.c b/firmware/targets/f3/f3-1/Src/stm32wbxx_hal_msp.c
index 4b2a90aa..c96a5dfa 100644
--- a/firmware/targets/f3/f3-1/Src/stm32wbxx_hal_msp.c
+++ b/firmware/targets/f3/f3-1/Src/stm32wbxx_hal_msp.c
@@ -74,6 +74,9 @@ void HAL_MspInit(void)
   HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 
   /* Peripheral interrupt init */
+  /* RCC_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(RCC_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(RCC_IRQn);
   /* HSEM_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(HSEM_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(HSEM_IRQn);
diff --git a/firmware/targets/f3/f3-1/Src/stm32wbxx_it.c b/firmware/targets/f3/f3-1/Src/stm32wbxx_it.c
index 8ae9d91b..89c1d754 100644
--- a/firmware/targets/f3/f3-1/Src/stm32wbxx_it.c
+++ b/firmware/targets/f3/f3-1/Src/stm32wbxx_it.c
@@ -59,6 +59,7 @@
 extern PCD_HandleTypeDef hpcd_USB_FS;
 extern ADC_HandleTypeDef hadc1;
 extern COMP_HandleTypeDef hcomp1;
+extern RTC_HandleTypeDef hrtc;
 extern TIM_HandleTypeDef htim1;
 extern TIM_HandleTypeDef htim2;
 extern TIM_HandleTypeDef htim17;
@@ -166,6 +167,34 @@ void DebugMon_Handler(void)
 /* please refer to the startup file (startup_stm32wbxx.s).                    */
 /******************************************************************************/
 
+/**
+  * @brief This function handles RTC tamper and time stamp, CSS on LSE interrupts through EXTI line 18.
+  */
+void TAMP_STAMP_LSECSS_IRQHandler(void)
+{
+  /* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 0 */
+  HAL_RCC_CSSCallback();
+  /* USER CODE END TAMP_STAMP_LSECSS_IRQn 0 */
+  /* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 1 */
+
+  /* USER CODE END TAMP_STAMP_LSECSS_IRQn 1 */
+}
+
+/**
+  * @brief This function handles RCC global interrupt.
+  */
+void RCC_IRQHandler(void)
+{
+  /* USER CODE BEGIN RCC_IRQn 0 */
+  if (!LL_RCC_LSE_IsReady()) {
+    HAL_RCC_CSSCallback();
+  }
+  /* USER CODE END RCC_IRQn 0 */
+  /* USER CODE BEGIN RCC_IRQn 1 */
+
+  /* USER CODE END RCC_IRQn 1 */
+}
+
 /**
   * @brief This function handles EXTI line1 interrupt.
   */
diff --git a/firmware/targets/f3/f3-1/f3-1.ioc b/firmware/targets/f3/f3-1/f3-1.ioc
index efc53a5f..ea8c87a3 100644
--- a/firmware/targets/f3/f3-1/f3-1.ioc
+++ b/firmware/targets/f3/f3-1/f3-1.ioc
@@ -44,6 +44,7 @@ PCC.Ble.PowerLevel=Min
 COMP1.Mode=COMP_POWERMODE_MEDIUMSPEED
 PB6.Signal=USART1_TX
 PB6.Mode=Asynchronous
+NVIC.TAMP_STAMP_LSECSS_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 SPI1.CalculateBaudRate=4.0 MBits/s
 PC3.Signal=GPIO_Analog
 PD0.Signal=GPIO_Output
@@ -72,6 +73,7 @@ ProjectManager.BackupPrevious=false
 VP_SYS_VS_tim17.Signal=SYS_VS_tim17
 PC4.GPIO_Label=CC1101_G0
 FREERTOS.HEAP_NUMBER=4
+RCC.LSE_Drive_Capability=RCC_LSEDRIVE_MEDIUMLOW
 PB1.GPIO_Label=BUTTON_DOWN
 NVIC.TIM2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true
 SPI1.DataSize=SPI_DATASIZE_8BIT
@@ -124,6 +126,7 @@ I2C1.CustomTiming=Disabled
 PA4.GPIO_Label=PA4
 ProjectManager.CustomerFirmwarePackage=
 PC4.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+NVIC.RCC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:false
 RCC.HSI48_VALUE=48000000
 PA6.GPIOParameters=GPIO_Label
 SH.GPXTI10.0=GPIO_EXTI10
@@ -399,6 +402,7 @@ Mcu.IP14=SPI1
 PB4.Mode=Full_Duplex_Master
 Mcu.IP13=RTC
 Mcu.IP16=SYS
+RCC.LSE_Timout=1000
 Mcu.IP15=SPI2
 PC14-OSC32_IN.Mode=LSE-External-Oscillator
 RCC.VCOInputFreq_Value=16000000
@@ -535,7 +539,7 @@ OSC_OUT.Locked=true
 PA4.GPIOParameters=GPIO_Label
 PH3-BOOT0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PB15.GPIOParameters=GPIO_Label
-RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EnableCSSLSE,EnbaleCSS,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIOscState,PLLM,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGCLockSelection,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
+RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EnableCSSLSE,EnbaleCSS,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_Drive_Capability,LSE_Timout,LSI_VALUE,MCO1PinFreq_Value,MSIOscState,PLLM,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGCLockSelection,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
 ProjectManager.AskForMigrate=true
 Mcu.Name=STM32WB55RGVx
 NVIC.SavedPendsvIrqHandlerGenerated=false
diff --git a/firmware/targets/f3/f3.ioc b/firmware/targets/f3/f3.ioc
index ab4ecb90..7dab2624 100644
--- a/firmware/targets/f3/f3.ioc
+++ b/firmware/targets/f3/f3.ioc
@@ -43,6 +43,7 @@ PCC.Ble.PowerLevel=Min
 COMP1.Mode=COMP_POWERMODE_MEDIUMSPEED
 PB6.Signal=USART1_TX
 PB6.Mode=Asynchronous
+NVIC.TAMP_STAMP_LSECSS_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 SPI1.CalculateBaudRate=4.0 MBits/s
 PC3.Signal=GPIO_Analog
 PD0.Signal=GPIO_Output
@@ -71,6 +72,7 @@ ProjectManager.BackupPrevious=false
 VP_SYS_VS_tim17.Signal=SYS_VS_tim17
 PC4.GPIO_Label=CC1101_G0
 FREERTOS.HEAP_NUMBER=4
+RCC.LSE_Drive_Capability=RCC_LSEDRIVE_MEDIUMLOW
 PB1.GPIO_Label=BUTTON_DOWN
 NVIC.TIM2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true
 SPI1.DataSize=SPI_DATASIZE_8BIT
@@ -124,6 +126,7 @@ I2C1.CustomTiming=Disabled
 PA4.GPIO_Label=PA4
 ProjectManager.CustomerFirmwarePackage=
 PC4.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+NVIC.RCC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:false
 RCC.HSI48_VALUE=48000000
 PC2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PA6.GPIOParameters=GPIO_Label
@@ -402,6 +405,7 @@ Mcu.IP14=SPI1
 PB4.Mode=Full_Duplex_Master
 Mcu.IP13=RTC
 Mcu.IP16=SYS
+RCC.LSE_Timout=1000
 Mcu.IP15=SPI2
 PC14-OSC32_IN.Mode=LSE-External-Oscillator
 RCC.VCOInputFreq_Value=16000000
@@ -537,7 +541,7 @@ OSC_OUT.Locked=true
 PA4.GPIOParameters=GPIO_Label
 PC2.GPIO_PuPd=GPIO_PULLUP
 PB15.GPIOParameters=GPIO_Label
-RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EnableCSSLSE,EnbaleCSS,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIOscState,PLLM,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGCLockSelection,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
+RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EnableCSSLSE,EnbaleCSS,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_Drive_Capability,LSE_Timout,LSI_VALUE,MCO1PinFreq_Value,MSIOscState,PLLM,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGCLockSelection,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
 ProjectManager.AskForMigrate=true
 Mcu.Name=STM32WB55RGVx
 NVIC.SavedPendsvIrqHandlerGenerated=false