[FL-2392] FuriHal: refactor interrupts subsystem (#1066)
* FuriHal: refactor interrupts subsystem * Furi,FuriHal: gather all ISRs under interrupt API, improve crtitical section and cleanup garbage * FuriHal: mirgate ipcc and hsem to LL * Format Sources * FuriHal,BleGlue: move to new critical section * Format Sources * FuriHal: correct flash locking * FuriHal: replace critical section with interrupt disable in OS routine, minor fixex
This commit is contained in:
@@ -1,126 +1,5 @@
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/**
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******************************************************************************
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* @file system_stm32wbxx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32wbxx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the MSI (4 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | MSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* PLL_M | 1
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*-----------------------------------------------------------------------------
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* PLL_N | 8
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*-----------------------------------------------------------------------------
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* PLL_P | 7
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*-----------------------------------------------------------------------------
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* PLL_Q | 2
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*-----------------------------------------------------------------------------
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* PLL_R | 2
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*-----------------------------------------------------------------------------
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* PLLSAI1_P | NA
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*-----------------------------------------------------------------------------
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* PLLSAI1_Q | NA
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*-----------------------------------------------------------------------------
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* PLLSAI1_R | NA
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32WBxx_system
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* @{
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*/
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/** @addtogroup stm32WBxx_System_Private_Includes
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* @{
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*/
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#include "stm32wbxx.h"
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#if !defined(HSE_VALUE)
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#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined(MSI_VALUE)
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#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
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#endif /* MSI_VALUE */
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#if !defined(HSI_VALUE)
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#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#if !defined(LSI_VALUE)
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#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
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#endif /* LSI_VALUE */
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#if !defined(LSE_VALUE)
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#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
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#endif /* LSE_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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@@ -131,21 +10,7 @@
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#define VECT_TAB_BASE_ADDRESS \
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SRAM1_BASE /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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@@ -179,30 +44,6 @@ const uint32_t MSIRangeTable[16UL] = {
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0UL,
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0UL}; /* 0UL values are incorrect cases */
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#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
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const uint32_t SmpsPrescalerTable[4UL][6UL] = {
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{1UL, 3UL, 2UL, 2UL, 1UL, 2UL},
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{2UL, 6UL, 4UL, 3UL, 2UL, 4UL},
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{4UL, 12UL, 8UL, 6UL, 4UL, 8UL},
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{4UL, 12UL, 8UL, 6UL, 4UL, 8UL}};
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#endif
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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@@ -254,118 +95,3 @@ void SystemInit(void) {
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
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* 32 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void) {
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uint32_t tmp, msirange, pllvco, pllr, pllsource, pllm;
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/* Get MSI Range frequency--------------------------------------------------*/
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/*MSI frequency range in Hz*/
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msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
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/* Get SYSCLK source -------------------------------------------------------*/
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switch(RCC->CFGR & RCC_CFGR_SWS) {
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case 0x00: /* MSI used as system clock source */
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SystemCoreClock = msirange;
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break;
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case 0x04: /* HSI used as system clock source */
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/* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
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if(pllsource == 0x02UL) /* HSI used as PLL clock source */
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{
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pllvco = (HSI_VALUE / pllm);
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} else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
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{
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pllvco = (HSE_VALUE / pllm);
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} else /* MSI used as PLL clock source */
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{
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pllvco = (msirange / pllm);
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
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SystemCoreClock = pllvco / pllr;
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break;
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default:
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SystemCoreClock = msirange;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK1 prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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/* HCLK clock frequency */
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SystemCoreClock = SystemCoreClock / tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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