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[FL-2392] FuriHal: refactor interrupts subsystem (#1066)

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* FuriHal: refactor interrupts subsystem

* Furi,FuriHal: gather all ISRs under interrupt API, improve crtitical section and cleanup garbage

* FuriHal: mirgate ipcc and hsem to LL

* Format Sources

* FuriHal,BleGlue: move to new critical section

* Format Sources

* FuriHal: correct flash locking

* FuriHal: replace critical section with interrupt disable in OS routine, minor fixex
This commit is contained in:
あく
2022-03-29 20:37:23 +03:00
committed by GitHub
parent bdba15b366
commit 489caa8e77
27 changed files with 360 additions and 715 deletions
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206
firmware/targets/f7/furi_hal/furi_hal_interrupt.c
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@@ -3,153 +3,201 @@
#include <furi.h>
#include <main.h>
#include <stm32wbxx.h>
#include <stm32wbxx_ll_tim.h>
#define TAG "FuriHalInterrupt"
volatile FuriHalInterruptISR furi_hal_tim_tim2_isr = NULL;
volatile FuriHalInterruptISR furi_hal_tim_tim1_isr = NULL;
#define FURI_HAL_INTERRUPT_DEFAULT_PRIORITY 5
#define FURI_HAL_INTERRUPT_DMA_COUNT 2
#define FURI_HAL_INTERRUPT_DMA_CHANNELS_COUNT 8
typedef struct {
FuriHalInterruptISR isr;
void* context;
} FuriHalInterruptISRPair;
volatile FuriHalInterruptISR furi_hal_dma_channel_isr[FURI_HAL_INTERRUPT_DMA_COUNT]
[FURI_HAL_INTERRUPT_DMA_CHANNELS_COUNT] = {0};
FuriHalInterruptISRPair furi_hal_interrupt_isr[FuriHalInterruptIdMax] = {0};
const IRQn_Type furi_hal_interrupt_irqn[FuriHalInterruptIdMax] = {
// TIM1, TIM16, TIM17
[FuriHalInterruptIdTim1TrgComTim17] = TIM1_TRG_COM_TIM17_IRQn,
[FuriHalInterruptIdTim1Cc] = TIM1_CC_IRQn,
[FuriHalInterruptIdTim1UpTim16] = TIM1_UP_TIM16_IRQn,
// TIM2
[FuriHalInterruptIdTIM2] = TIM2_IRQn,
// DMA1
[FuriHalInterruptIdDma1Ch1] = DMA1_Channel1_IRQn,
[FuriHalInterruptIdDma1Ch2] = DMA1_Channel2_IRQn,
[FuriHalInterruptIdDma1Ch3] = DMA1_Channel3_IRQn,
[FuriHalInterruptIdDma1Ch4] = DMA1_Channel4_IRQn,
[FuriHalInterruptIdDma1Ch5] = DMA1_Channel5_IRQn,
[FuriHalInterruptIdDma1Ch6] = DMA1_Channel6_IRQn,
[FuriHalInterruptIdDma1Ch7] = DMA1_Channel7_IRQn,
// DMA2
[FuriHalInterruptIdDma2Ch1] = DMA2_Channel1_IRQn,
[FuriHalInterruptIdDma2Ch2] = DMA2_Channel2_IRQn,
[FuriHalInterruptIdDma2Ch3] = DMA2_Channel3_IRQn,
[FuriHalInterruptIdDma2Ch4] = DMA2_Channel4_IRQn,
[FuriHalInterruptIdDma2Ch5] = DMA2_Channel5_IRQn,
[FuriHalInterruptIdDma2Ch6] = DMA2_Channel6_IRQn,
[FuriHalInterruptIdDma2Ch7] = DMA2_Channel7_IRQn,
// RCC
[FuriHalInterruptIdRcc] = RCC_IRQn,
// COMP
[FuriHalInterruptIdCOMP] = COMP_IRQn,
// HSEM
[FuriHalInterruptIdHsem] = HSEM_IRQn,
};
__attribute__((always_inline)) static inline void
furi_hal_interrupt_call(FuriHalInterruptId index) {
furi_assert(furi_hal_interrupt_isr[index].isr);
furi_hal_interrupt_isr[index].isr(furi_hal_interrupt_isr[index].context);
}
__attribute__((always_inline)) static inline void
furi_hal_interrupt_enable(FuriHalInterruptId index, uint16_t priority) {
NVIC_SetPriority(
furi_hal_interrupt_irqn[index],
NVIC_EncodePriority(NVIC_GetPriorityGrouping(), priority, 0));
NVIC_EnableIRQ(furi_hal_interrupt_irqn[index]);
}
__attribute__((always_inline)) static inline void
furi_hal_interrupt_disable(FuriHalInterruptId index) {
NVIC_DisableIRQ(furi_hal_interrupt_irqn[index]);
}
void furi_hal_interrupt_init() {
NVIC_SetPriority(RCC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
NVIC_EnableIRQ(RCC_IRQn);
NVIC_SetPriority(
TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
NVIC_SetPriority(HSEM_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
HAL_NVIC_EnableIRQ(HSEM_IRQn);
FURI_LOG_I(TAG, "Init OK");
}
void furi_hal_interrupt_set_timer_isr(TIM_TypeDef* timer, FuriHalInterruptISR isr) {
if(timer == TIM2) {
if(isr) {
furi_assert(furi_hal_tim_tim2_isr == NULL);
} else {
furi_assert(furi_hal_tim_tim2_isr != NULL);
}
furi_hal_tim_tim2_isr = isr;
} else if(timer == TIM1) {
if(isr) {
furi_assert(furi_hal_tim_tim1_isr == NULL);
} else {
furi_assert(furi_hal_tim_tim1_isr != NULL);
}
furi_hal_tim_tim1_isr = isr;
} else {
furi_crash(NULL);
}
void furi_hal_interrupt_set_isr(FuriHalInterruptId index, FuriHalInterruptISR isr, void* context) {
furi_hal_interrupt_set_isr_ex(index, FURI_HAL_INTERRUPT_DEFAULT_PRIORITY, isr, context);
}
void furi_hal_interrupt_set_dma_channel_isr(
DMA_TypeDef* dma,
uint32_t channel,
FuriHalInterruptISR isr) {
--channel; // Pascal
furi_check(dma);
furi_check(channel < FURI_HAL_INTERRUPT_DMA_CHANNELS_COUNT);
if(dma == DMA1) {
furi_hal_dma_channel_isr[0][channel] = isr;
} else if(dma == DMA2) {
furi_hal_dma_channel_isr[1][channel] = isr;
void furi_hal_interrupt_set_isr_ex(
FuriHalInterruptId index,
uint16_t priority,
FuriHalInterruptISR isr,
void* context) {
furi_assert(index < FuriHalInterruptIdMax);
furi_assert(priority < 15);
furi_assert(furi_hal_interrupt_irqn[index]);
if(isr) {
// Pre ISR set
furi_assert(furi_hal_interrupt_isr[index].isr == NULL);
} else {
furi_crash(NULL);
// Pre ISR clear
furi_assert(furi_hal_interrupt_isr[index].isr != NULL);
furi_hal_interrupt_disable(index);
}
furi_hal_interrupt_isr[index].isr = isr;
furi_hal_interrupt_isr[index].context = context;
__DMB();
if(isr) {
// Post ISR set
furi_hal_interrupt_enable(index, priority);
} else {
// Post ISR clear
}
}
/* Timer 2 */
void TIM2_IRQHandler(void) {
if(furi_hal_tim_tim2_isr) {
furi_hal_tim_tim2_isr();
}
furi_hal_interrupt_call(FuriHalInterruptIdTIM2);
}
/* Timer 1 Update */
void TIM1_UP_TIM16_IRQHandler(void) {
if(furi_hal_tim_tim1_isr) {
furi_hal_tim_tim1_isr();
}
furi_hal_interrupt_call(FuriHalInterruptIdTim1UpTim16);
}
void TIM1_TRG_COM_TIM17_IRQHandler(void) {
furi_hal_interrupt_call(FuriHalInterruptIdTim1TrgComTim17);
}
void TIM1_CC_IRQHandler(void) {
furi_hal_interrupt_call(FuriHalInterruptIdTim1Cc);
}
/* DMA 1 */
void DMA1_Channel1_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][0]) furi_hal_dma_channel_isr[0][0]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch1);
}
void DMA1_Channel2_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][1]) furi_hal_dma_channel_isr[0][1]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch2);
}
void DMA1_Channel3_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][2]) furi_hal_dma_channel_isr[0][2]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch3);
}
void DMA1_Channel4_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][3]) furi_hal_dma_channel_isr[0][3]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch4);
}
void DMA1_Channel5_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][4]) furi_hal_dma_channel_isr[0][4]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch5);
}
void DMA1_Channel6_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][5]) furi_hal_dma_channel_isr[0][5]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch6);
}
void DMA1_Channel7_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][6]) furi_hal_dma_channel_isr[0][6]();
}
void DMA1_Channel8_IRQHandler(void) {
if(furi_hal_dma_channel_isr[0][7]) furi_hal_dma_channel_isr[0][7]();
furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch7);
}
/* DMA 2 */
void DMA2_Channel1_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][0]) furi_hal_dma_channel_isr[1][0]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch1);
}
void DMA2_Channel2_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][1]) furi_hal_dma_channel_isr[1][1]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch2);
}
void DMA2_Channel3_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][2]) furi_hal_dma_channel_isr[1][2]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch3);
}
void DMA2_Channel4_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][3]) furi_hal_dma_channel_isr[1][3]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch4);
}
void DMA2_Channel5_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][4]) furi_hal_dma_channel_isr[1][4]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch5);
}
void DMA2_Channel6_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][5]) furi_hal_dma_channel_isr[1][5]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch6);
}
void DMA2_Channel7_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][6]) furi_hal_dma_channel_isr[1][6]();
furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch7);
}
void DMA2_Channel8_IRQHandler(void) {
if(furi_hal_dma_channel_isr[1][7]) furi_hal_dma_channel_isr[1][7]();
void HSEM_IRQHandler(void) {
furi_hal_interrupt_call(FuriHalInterruptIdHsem);
}
void TAMP_STAMP_LSECSS_IRQHandler(void) {
@@ -165,6 +213,7 @@ void TAMP_STAMP_LSECSS_IRQHandler(void) {
}
void RCC_IRQHandler(void) {
furi_hal_interrupt_call(FuriHalInterruptIdRcc);
}
void NMI_Handler(void) {
@@ -193,3 +242,26 @@ void UsageFault_Handler(void) {
void DebugMon_Handler(void) {
}
#include "usbd_core.h"
extern usbd_device udev;
extern void HW_IPCC_Tx_Handler();
extern void HW_IPCC_Rx_Handler();
void SysTick_Handler(void) {
HAL_IncTick();
}
void USB_LP_IRQHandler(void) {
usbd_poll(&udev);
}
void IPCC_C1_TX_IRQHandler(void) {
HW_IPCC_Tx_Handler();
}
void IPCC_C1_RX_IRQHandler(void) {
HW_IPCC_Rx_Handler();
}