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[FL-950] CC1101 Stage1, SPI Refactoring, Drivers layer (#386)

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* API HAL SPI: refactoring, split into layers, prepare ST HAL separation. API HAL SubGhz: initialize on start. Drivers: add basic cc1101 driver. Update API usage. Debug: increase max debugger port speed. Remove subghz apps.
* CC1101: chip status handling. ApiHalSpi: increase SubGhz bus speed to 8mhz. F4: backport subghz initialization.
* Api Hal SubGhz: rx path and frequency. CC1101: frequency control.
* SubGhz Application: basic tests
* SubGhz app: tone and packet test. API HAL SUBGHZ: update configs, add missing bits and pieces.
This commit is contained in:
あく
2021-03-31 20:52:26 +03:00
committed by GitHub
parent 5309bfae41
commit 5439e232cc
60 changed files with 2364 additions and 2500 deletions
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6
debug/stm32wbx.cfg
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@@ -55,7 +55,7 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
#
# Note that there is a pretty wide band where things are
# more or less stable, see http://openocd.zylin.com/#/c/3366/
adapter speed 8000
adapter speed 24000
adapter srst delay 100
if {[using_jtag]} {
@@ -77,12 +77,12 @@ $_TARGETNAME configure -event reset-init {
mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
# Boost JTAG frequency
adapter speed 8000
adapter speed 24000
}
$_TARGETNAME configure -event reset-start {
# Reset clock is MSI (4 MHz)
adapter speed 8000
adapter speed 24000
}
$_TARGETNAME configure -event examine-end {