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[FL-1472, FL-1596, FL-1673] IRDA: stability improvements (#655)

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- Restrict with 31 bytes length for remote and signal name
- Don't stuck for 0 PWM cycle timings
- Support timings > 65535 PWM cycles
- Fix remote file open error
- Add IRDA TX debug redirect
- Add remote parse error print, improve parsing, support tabs
- Fix stucks with uncorrect RAW signal values, long strings in remote file, etc
- Fix HAL signals capturing (save previous read value)
- Fix leak in case of failed parsing
This commit is contained in:
Albert Kharisov
2021-08-19 03:18:42 +03:00
committed by GitHub
parent 9d38f28de7
commit 5f6aff2255
19 changed files with 347 additions and 177 deletions
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143
firmware/targets/f6/furi-hal/furi-hal-irda.c
View File

@@ -17,6 +17,13 @@
#include <main.h>
#include <furi-hal-pwm.h>
#define IRDA_TX_DEBUG 0
#if IRDA_TX_DEBUG == 1
#define gpio_irda_tx gpio_irda_tx_debug
const GpioPin gpio_irda_tx_debug = {.port = GPIOA, .pin = GPIO_PIN_7};
#endif
#define IRDA_TIM_TX_DMA_BUFFER_SIZE 200
#define IRDA_POLARITY_SHIFT 1
@@ -46,6 +53,9 @@ typedef struct {
void* signal_sent_context;
IrdaTxBuf buffer[2];
osSemaphoreId_t stop_semaphore;
uint32_t tx_timing_rest_duration; /** if timing is too long (> 0xFFFF), send it in few iterations */
bool tx_timing_rest_level;
FuriHalIrdaTxGetDataState tx_timing_rest_status;
} IrdaTimTx;
typedef enum {
@@ -62,7 +72,7 @@ static volatile IrdaState furi_hal_irda_state = IrdaStateIdle;
static IrdaTimTx irda_tim_tx;
static IrdaTimRx irda_tim_rx;
static bool furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift);
static void furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift);
static void furi_hal_irda_async_tx_free_resources(void);
static void furi_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift);
static void furi_hal_irda_tx_dma_set_buffer(uint8_t buf_num);
@@ -72,6 +82,7 @@ static void furi_hal_irda_tx_dma_polarity_isr();
static void furi_hal_irda_tx_dma_isr();
static void furi_hal_irda_tim_rx_isr() {
static uint32_t previous_captured_ch2 = 0;
/* Timeout */
if(LL_TIM_IsActiveFlag_CC3(TIM2)) {
@@ -97,7 +108,7 @@ static void furi_hal_irda_tim_rx_isr() {
if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC1S)) {
/* Low pin level is a Mark state of IRDA signal. Invert level for further processing. */
uint32_t duration = LL_TIM_IC_GetCaptureCH1(TIM2) - LL_TIM_IC_GetCaptureCH2(TIM2);
uint32_t duration = LL_TIM_IC_GetCaptureCH1(TIM2) - previous_captured_ch2;
if (irda_tim_rx.capture_callback)
irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 1, duration);
} else {
@@ -113,6 +124,7 @@ static void furi_hal_irda_tim_rx_isr() {
if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC2S)) {
/* High pin level is a Space state of IRDA signal. Invert level for further processing. */
uint32_t duration = LL_TIM_IC_GetCaptureCH2(TIM2);
previous_captured_ch2 = duration;
if (irda_tim_rx.capture_callback)
irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 0, duration);
} else {
@@ -258,14 +270,10 @@ static void furi_hal_irda_tx_dma_isr() {
if (irda_tim_tx.buffer[buf_num].last_packet_end) {
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
} else if (!irda_tim_tx.buffer[buf_num].packet_end || (furi_hal_irda_state == IrdaStateAsyncTx)) {
bool result = furi_hal_irda_tx_fill_buffer(next_buf_num, 0);
furi_hal_irda_tx_fill_buffer(next_buf_num, 0);
if (irda_tim_tx.buffer[next_buf_num].last_packet_end) {
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
}
if (!result) {
furi_assert(0);
furi_hal_irda_state = IrdaStateAsyncTxStopReq;
}
} else if (furi_hal_irda_state == IrdaStateAsyncTxStopReq) {
/* fallthrough */
} else {
@@ -291,7 +299,7 @@ static void furi_hal_irda_tx_dma_isr() {
/* if it's not end of the packet - continue receiving */
furi_hal_irda_tx_dma_set_buffer(next_buf_num);
}
if (irda_tim_tx.signal_sent_callback) {
if (irda_tim_tx.signal_sent_callback && irda_tim_tx.buffer[buf_num].packet_end && (furi_hal_irda_state != IrdaStateAsyncTxStopped)) {
irda_tim_tx.signal_sent_callback(irda_tim_tx.signal_sent_context);
}
}
@@ -309,6 +317,16 @@ static void furi_hal_irda_configure_tim_pwm_tx(uint32_t freq, float duty_cycle)
LL_TIM_SetCounterMode(TIM1, LL_TIM_COUNTERMODE_UP);
LL_TIM_EnableARRPreload(TIM1);
LL_TIM_SetAutoReload(TIM1, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIM1), freq));
#if IRDA_TX_DEBUG == 1
LL_TIM_OC_SetCompareCH1(TIM1, ( (LL_TIM_GetAutoReload(TIM1) + 1 ) * (1 - duty_cycle)));
LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH1);
/* LL_TIM_OCMODE_PWM2 set by DMA */
LL_TIM_OC_SetMode(TIM1, LL_TIM_CHANNEL_CH1, LL_TIM_OCMODE_FORCED_INACTIVE);
LL_TIM_OC_SetPolarity(TIM1, LL_TIM_CHANNEL_CH1N, LL_TIM_OCPOLARITY_HIGH);
LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH1);
LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH1N);
LL_TIM_DisableIT_CC1(TIM1);
#else
LL_TIM_OC_SetCompareCH3(TIM1, ( (LL_TIM_GetAutoReload(TIM1) + 1 ) * (1 - duty_cycle)));
LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH3);
/* LL_TIM_OCMODE_PWM2 set by DMA */
@@ -317,6 +335,7 @@ static void furi_hal_irda_configure_tim_pwm_tx(uint32_t freq, float duty_cycle)
LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH3);
LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH3N);
LL_TIM_DisableIT_CC3(TIM1);
#endif
LL_TIM_DisableMasterSlaveMode(TIM1);
LL_TIM_EnableAllOutputs(TIM1);
LL_TIM_DisableIT_UPDATE(TIM1);
@@ -330,7 +349,11 @@ static void furi_hal_irda_configure_tim_cmgr2_dma_tx(void) {
LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
LL_DMA_InitTypeDef dma_config = {0};
#if IRDA_TX_DEBUG == 1
dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->CCMR1);
#else
dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->CCMR2);
#endif
dma_config.MemoryOrM2MDstAddress = (uint32_t) NULL;
dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
dma_config.Mode = LL_DMA_MODE_NORMAL;
@@ -399,7 +422,7 @@ static void furi_hal_irda_tx_fill_buffer_last(uint8_t buf_num) {
irda_tim_tx.buffer[buf_num].packet_end = true;
}
static bool furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift) {
static void furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift) {
furi_assert(buf_num < 2);
furi_assert(furi_hal_irda_state != IrdaStateAsyncRx);
furi_assert(furi_hal_irda_state < IrdaStateMAX);
@@ -418,28 +441,53 @@ static bool furi_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift
}
for (*size = 0; (*size < IRDA_TIM_TX_DMA_BUFFER_SIZE) && (status == FuriHalIrdaTxGetDataStateOk); ++(*size), ++polarity_counter) {
status = irda_tim_tx.data_callback(irda_tim_tx.data_context, &duration, &level);
if (status == FuriHalIrdaTxGetDataStateError) {
furi_assert(0);
break;
if (irda_tim_tx.tx_timing_rest_duration > 0) {
if (irda_tim_tx.tx_timing_rest_duration > 0xFFFF) {
buffer->data[*size] = 0xFFFF;
status = FuriHalIrdaTxGetDataStateOk;
} else {
buffer->data[*size] = irda_tim_tx.tx_timing_rest_duration;
status = irda_tim_tx.tx_timing_rest_status;
}
irda_tim_tx.tx_timing_rest_duration -= buffer->data[*size];
buffer->polarity[polarity_counter] = irda_tim_tx.tx_timing_rest_level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
continue;
}
status = irda_tim_tx.data_callback(irda_tim_tx.data_context, &duration, &level);
uint32_t num_of_impulses = roundf(duration / irda_tim_tx.cycle_duration);
if ((buffer->data[*size] + num_of_impulses - 1) > 0xFFFF) {
furi_assert(0);
status = FuriHalIrdaTxGetDataStateError;
break;
if (num_of_impulses == 0) {
if ((*size == 0) && (status == FuriHalIrdaTxGetDataStateDone)) {
/* if this is one sample in current buffer, but we
* have more to send - continue
*/
status = FuriHalIrdaTxGetDataStateOk;
}
--(*size);
--polarity_counter;
} else if ((num_of_impulses - 1) > 0xFFFF) {
irda_tim_tx.tx_timing_rest_duration = num_of_impulses - 1;
irda_tim_tx.tx_timing_rest_status = status;
irda_tim_tx.tx_timing_rest_level = level;
buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
buffer->data[*size] = 0xFFFF;
status = FuriHalIrdaTxGetDataStateOk;
} else {
buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
buffer->data[*size] = num_of_impulses - 1;
}
buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
buffer->data[*size] = num_of_impulses - 1;
}
buffer->last_packet_end = (status == FuriHalIrdaTxGetDataStateLastDone);
buffer->packet_end = buffer->last_packet_end || (status == FuriHalIrdaTxGetDataStateDone);
return status != FuriHalIrdaTxGetDataStateError;
if (*size == 0) {
buffer->data[0] = 0; // 1 pulse
buffer->polarity[0] = IRDA_TX_CCMR_LOW;
buffer->size = 1;
}
}
static void furi_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift) {
@@ -505,10 +553,9 @@ static void furi_hal_irda_async_tx_free_resources(void) {
irda_tim_tx.buffer[1].polarity = NULL;
}
bool furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
if ((duty_cycle > 1) || (duty_cycle < 0) || (freq > 40000) || (freq < 10000) || (irda_tim_tx.data_callback == NULL)) {
furi_assert(0);
return false;
void furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
if ((duty_cycle > 1) || (duty_cycle <= 0) || (freq > IRDA_MAX_FREQUENCY) || (freq < IRDA_MIN_FREQUENCY) || (irda_tim_tx.data_callback == NULL)) {
furi_check(0);
}
furi_assert(furi_hal_irda_state == IrdaStateIdle);
@@ -527,37 +574,31 @@ bool furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
irda_tim_tx.stop_semaphore = osSemaphoreNew(1, 0, NULL);
irda_tim_tx.cycle_duration = 1000000.0 / freq;
irda_tim_tx.tx_timing_rest_duration = 0;
bool result = furi_hal_irda_tx_fill_buffer(0, IRDA_POLARITY_SHIFT);
furi_hal_irda_tx_fill_buffer(0, IRDA_POLARITY_SHIFT);
if (result) {
furi_hal_irda_configure_tim_pwm_tx(freq, duty_cycle);
furi_hal_irda_configure_tim_cmgr2_dma_tx();
furi_hal_irda_configure_tim_rcr_dma_tx();
furi_hal_irda_tx_dma_set_polarity(0, IRDA_POLARITY_SHIFT);
furi_hal_irda_tx_dma_set_buffer(0);
furi_hal_irda_configure_tim_pwm_tx(freq, duty_cycle);
furi_hal_irda_configure_tim_cmgr2_dma_tx();
furi_hal_irda_configure_tim_rcr_dma_tx();
furi_hal_irda_tx_dma_set_polarity(0, IRDA_POLARITY_SHIFT);
furi_hal_irda_tx_dma_set_buffer(0);
furi_hal_irda_state = IrdaStateAsyncTx;
furi_hal_irda_state = IrdaStateAsyncTx;
LL_TIM_ClearFlag_UPDATE(TIM1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
delay_us(5);
LL_TIM_GenerateEvent_UPDATE(TIM1); /* DMA -> TIMx_RCR */
delay_us(5);
LL_GPIO_ResetOutputPin(gpio_irda_tx.port, gpio_irda_tx.pin); /* when disable it prevents false pulse */
hal_gpio_init_ex(&gpio_irda_tx, GpioModeAltFunctionPushPull, GpioPullUp, GpioSpeedHigh, GpioAltFn1TIM1);
LL_TIM_ClearFlag_UPDATE(TIM1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
delay_us(5);
LL_TIM_GenerateEvent_UPDATE(TIM1); /* DMA -> TIMx_RCR */
delay_us(5);
LL_GPIO_ResetOutputPin(gpio_irda_tx.port, gpio_irda_tx.pin); /* when disable it prevents false pulse */
hal_gpio_init_ex(&gpio_irda_tx, GpioModeAltFunctionPushPull, GpioPullUp, GpioSpeedHigh, GpioAltFn1TIM1);
__disable_irq();
LL_TIM_GenerateEvent_UPDATE(TIM1); /* TIMx_RCR -> Repetition counter */
LL_TIM_EnableCounter(TIM1);
__enable_irq();
} else {
furi_hal_irda_async_tx_free_resources();
}
return result;
__disable_irq();
LL_TIM_GenerateEvent_UPDATE(TIM1); /* TIMx_RCR -> Repetition counter */
LL_TIM_EnableCounter(TIM1);
__enable_irq();
}
void furi_hal_irda_async_tx_wait_termination(void) {

8
firmware/targets/furi-hal-include/furi-hal-irda.h
View File

@@ -7,8 +7,10 @@
extern "C" {
#endif
#define IRDA_MAX_FREQUENCY 56000
#define IRDA_MIN_FREQUENCY 10000
typedef enum {
FuriHalIrdaTxGetDataStateError, /* An error occured during transmission */
FuriHalIrdaTxGetDataStateOk, /* New data obtained */
FuriHalIrdaTxGetDataStateDone, /* New data obtained, and this is end of package */
FuriHalIrdaTxGetDataStateLastDone, /* New data obtained, and this is end of package and no more data available */
@@ -103,10 +105,8 @@ void furi_hal_irda_async_tx_set_data_isr_callback(FuriHalIrdaTxGetDataISRCallbac
*
* @param[in] freq - frequency for PWM
* @param[in] duty_cycle - duty cycle for PWM
* @return true if transmission successfully started, false otherwise.
* If start failed no need to free resources.
*/
bool furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle);
void furi_hal_irda_async_tx_start(uint32_t freq, float duty_cycle);
/**
* Stop IR asynchronous transmission and free resources.