SubGhz: fix cc1101_read_fifo func (#2379)
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@ -150,9 +150,8 @@ uint8_t cc1101_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* data, uint
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uint8_t cc1101_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* data, uint8_t* size) {
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uint8_t cc1101_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* data, uint8_t* size) {
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uint8_t buff_tx[64];
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uint8_t buff_trx[2];
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buff_tx[0] = CC1101_FIFO | CC1101_READ | CC1101_BURST;
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buff_trx[0] = CC1101_FIFO | CC1101_READ | CC1101_BURST;
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uint8_t buff_rx[2];
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// Start transaction
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// Start transaction
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// Wait IC to become ready
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// Wait IC to become ready
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@ -160,15 +159,15 @@ uint8_t cc1101_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* data, uint8_t* si
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;
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// First byte - packet length
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// First byte - packet length
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furi_hal_spi_bus_trx(handle, buff_tx, buff_rx, 2, CC1101_TIMEOUT);
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furi_hal_spi_bus_trx(handle, buff_trx, buff_trx, 2, CC1101_TIMEOUT);
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// Check that the packet is placed in the receive buffer
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// Check that the packet is placed in the receive buffer
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if(buff_rx[1] > 64) {
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if(buff_trx[1] > 64) {
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*size = 64;
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*size = 64;
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} else {
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} else {
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*size = buff_rx[1];
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*size = buff_trx[1];
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}
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}
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furi_hal_spi_bus_trx(handle, &buff_tx[1], data, *size, CC1101_TIMEOUT);
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furi_hal_spi_bus_trx(handle, NULL, data, *size, CC1101_TIMEOUT);
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return *size;
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return *size;
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}
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}
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