[FL-1815, FL-1851, FL-1856] SubGhz: preparation for certification, add deleting stored signals and rename file in SubGHz app (#714)
* [FL-1811] FuriHal: move core2 startup to hal init stage, prevent working with flash controller till core2 startup finish. #704 * SubGhz: fix GO0 low on last hop transmission, decreased DutyCycle in tests * SubGhz: test_static fix max 5 sec in transmission mode, DutyCycle <23% * [FL-1815] SubGhz: prohibiting transmission if it is not within the permitted range for the given region * SubGhz: fix F7 furi-hal-subghz * SubGhz: fix logic working tests * SubGhz: fix princeton encoder for test * SubGhz: add log princeton encoder * [FL-1856] Subghz: fix output a double error if the file cannot be opened * [FL-1851] SubGhz: add deleting Stored Signals in SubGHz App * SubGhz: add rename file SubGhz app * SubGhz: update stats message in princeton * SubGhz: correct spelling * SubGhz: fix FM config, add hardware signal processing less than 16 μs, add added filter for processing short signals * SubGhz: add Scher-Khan MAGICAR Dinamic protocol * SubGhz: sync fury targets Co-authored-by: あく <alleteam@gmail.com>
This commit is contained in:
Skorpionm
GitHub
@@ -1,4 +1,5 @@
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#include "furi-hal-subghz.h"
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#include "furi-hal-version.h"
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#include <furi-hal-gpio.h>
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#include <furi-hal-spi.h>
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@@ -10,6 +11,7 @@
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#include <stdio.h>
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static volatile SubGhzState furi_hal_subghz_state = SubGhzStateInit;
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static volatile SubGhzRegulation furi_hal_subghz_regulation = SubGhzRegulationTxRx;
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static const uint8_t furi_hal_subghz_preset_ook_270khz_async_regs[][2] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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@@ -41,11 +43,11 @@ static const uint8_t furi_hal_subghz_preset_ook_270khz_async_regs[][2] = {
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCTRL0,
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{CC1101_AGCCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCTRL1,
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{CC1101_AGCCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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{CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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@@ -99,11 +101,15 @@ static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
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0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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// {CC1101_AGCTRL0,0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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// {CC1101_AGCTRL1,0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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// {CC1101_AGCCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
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{CC1101_AGCCTRL0,
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0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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{CC1101_AGCCTRL1,
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0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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@@ -131,23 +137,21 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
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/* GPIO GD0 */
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{CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
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/* FIFO and internals */
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{CC1101_FIFOTHR, 0x47}, // The only important bit is ADC_RETENTION
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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{CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x02},
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{CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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{CC1101_MDMCFG3, 0x8B}, // Data rate is 19.5885 kBaud
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{CC1101_MDMCFG4, 0x69}, // Rx BW filter is 270.833333 kHz
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/* Packet engine */
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{CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
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{CC1101_PKTCTRL1, 0x04},
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{CC1101_DEVIATN, 0x47}, //Deviation 47.607422 khz
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// // Modem Configuration
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{CC1101_MDMCFG0, 0x00},
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{CC1101_MDMCFG1, 0x2},
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{CC1101_MDMCFG2, 0x4}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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{CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
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{CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
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//{ CC1101_DEVIATN, 0x14 }, //Deviation 4.760742 kHz
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{CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
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/* Main Radio Control State Machine */
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{CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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@@ -157,18 +161,18 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
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0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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{CC1101_AGCTRL0,
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0x40}, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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{CC1101_AGCTRL1,
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{CC1101_AGCCTRL0,
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0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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{CC1101_AGCCTRL1,
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0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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{CC1101_AGCTRL2, 0x03}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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{CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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{CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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{CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
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{CC1101_FREND1, 0xB6}, //
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{CC1101_FREND1, 0x56},
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/* Frequency Synthesizer Calibration, valid for 433.92 */
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{CC1101_FSCAL3, 0xE9},
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@@ -201,7 +205,9 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_patable[8] = {
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0x00,
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0x00,
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0x00,
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0x00};
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0x00
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};
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void furi_hal_subghz_init() {
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furi_assert(furi_hal_subghz_state == SubGhzStateInit);
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@@ -279,7 +285,7 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
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} else if(preset == FuriHalSubGhzPreset2FSKAsync) {
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
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}else {
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} else {
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furi_crash(NULL);
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}
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}
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@@ -356,10 +362,12 @@ void furi_hal_subghz_rx() {
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furi_hal_spi_device_return(device);
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}
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void furi_hal_subghz_tx() {
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bool furi_hal_subghz_tx() {
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if(furi_hal_subghz_regulation != SubGhzRegulationTxRx) return false;
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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cc1101_switch_to_tx(device);
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furi_hal_spi_device_return(device);
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return true;
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}
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float furi_hal_subghz_get_rssi() {
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@@ -383,6 +391,7 @@ bool furi_hal_subghz_is_frequency_valid(uint32_t value) {
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!(value >= 778999847 && value <= 928000000)) {
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return false;
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}
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return true;
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}
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@@ -403,6 +412,46 @@ uint32_t furi_hal_subghz_set_frequency_and_path(uint32_t value) {
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uint32_t furi_hal_subghz_set_frequency(uint32_t value) {
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const FuriHalSpiDevice* device = furi_hal_spi_device_get(FuriHalSpiDeviceIdSubGhz);
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//checking regional settings
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bool txrx = false;
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switch(furi_hal_version_get_hw_region()) {
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case FuriHalVersionRegionEuRu:
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//433,05..434,79; 868,15..868,55
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if(!(value >= 433050000 && value <= 434790000) &&
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!(value >= 868150000 && value <= 8680550000)) {
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} else {
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txrx = true;
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}
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break;
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case FuriHalVersionRegionUsCaAu:
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//304,10..315,25; 433,05..434,79; 915,00..928,00
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if(!(value >= 304100000 && value <= 315250000) &&
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!(value >= 433050000 && value <= 434790000) &&
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!(value >= 915000000 && value <= 928000000)) {
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} else {
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txrx = true;
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}
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break;
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case FuriHalVersionRegionJp:
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//312,00..315,25; 920,50..923,50
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if(!(value >= 312000000 && value <= 315250000) &&
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!(value >= 920500000 && value <= 923500000)) {
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} else {
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txrx = true;
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}
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break;
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default:
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txrx = true;
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break;
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}
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if(txrx) {
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furi_hal_subghz_regulation = SubGhzRegulationTxRx;
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} else {
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furi_hal_subghz_regulation = SubGhzRegulationOnlyRx;
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}
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uint32_t real_frequency = cc1101_set_frequency(device, value);
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cc1101_calibrate(device);
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@@ -480,7 +529,7 @@ void furi_hal_subghz_start_async_rx(FuriHalSubGhzCaptureCallback callback, void*
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TIM_InitStruct.Prescaler = 64 - 1;
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TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
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TIM_InitStruct.Autoreload = 0x7FFFFFFE;
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TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
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TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV4;
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LL_TIM_Init(TIM2, &TIM_InitStruct);
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// Timer: advanced
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@@ -503,7 +552,7 @@ void furi_hal_subghz_start_async_rx(FuriHalSubGhzCaptureCallback callback, void*
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LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_DIRECTTI);
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LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
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LL_TIM_IC_SetPolarity(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_POLARITY_RISING);
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LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_FILTER_FDIV1);
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LL_TIM_IC_SetFilter(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_IC_FILTER_FDIV32_N8);
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// ISR setup
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furi_hal_interrupt_set_timer_isr(TIM2, furi_hal_subghz_capture_ISR);
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@@ -608,6 +657,8 @@ static void furi_hal_subghz_async_tx_timer_isr() {
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if(LL_TIM_GetAutoReload(TIM2) == 0) {
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if(furi_hal_subghz_state == SubGhzStateAsyncTx) {
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furi_hal_subghz_state = SubGhzStateAsyncTxLast;
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//forcibly pulls the pin to the ground so that there is no carrier
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hal_gpio_init(&gpio_cc1101_g0, GpioModeInput, GpioPullDown, GpioSpeedLow);
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} else {
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furi_hal_subghz_state = SubGhzStateAsyncTxEnd;
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LL_TIM_DisableCounter(TIM2);
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@@ -616,10 +667,13 @@ static void furi_hal_subghz_async_tx_timer_isr() {
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}
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}
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void furi_hal_subghz_start_async_tx(FuriHalSubGhzAsyncTxCallback callback, void* context) {
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bool furi_hal_subghz_start_async_tx(FuriHalSubGhzAsyncTxCallback callback, void* context) {
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furi_assert(furi_hal_subghz_state == SubGhzStateIdle);
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furi_assert(callback);
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//If transmission is prohibited by regional settings
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if(furi_hal_subghz_regulation != SubGhzRegulationTxRx) return false;
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furi_hal_subghz_async_tx.callback = callback;
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furi_hal_subghz_async_tx.callback_context = context;
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@@ -694,6 +748,7 @@ void furi_hal_subghz_start_async_tx(FuriHalSubGhzAsyncTxCallback callback, void*
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LL_TIM_SetCounter(TIM2, 0);
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LL_TIM_EnableCounter(TIM2);
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return true;
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}
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bool furi_hal_subghz_is_async_tx_complete() {
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