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IRDA: Use DMA for async TX (#608)

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This commit is contained in:
Albert Kharisov
2021-08-06 00:11:35 +03:00
committed by GitHub
parent 9c38efd4ef
commit ba399abb5d
9 changed files with 657 additions and 162 deletions
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19
firmware/targets/f6/api-hal/api-hal-interrupt.c
View File

@@ -5,6 +5,7 @@
#include <stm32wbxx_ll_tim.h>
volatile ApiHalInterruptISR api_hal_tim_tim2_isr = NULL;
volatile ApiHalInterruptISR api_hal_tim_tim1_isr = NULL;
#define API_HAL_INTERRUPT_DMA_COUNT 2
#define API_HAL_INTERRUPT_DMA_CHANNELS_COUNT 8
@@ -32,6 +33,13 @@ void api_hal_interrupt_set_timer_isr(TIM_TypeDef* timer, ApiHalInterruptISR isr)
furi_assert(api_hal_tim_tim2_isr != NULL);
}
api_hal_tim_tim2_isr = isr;
} else if (timer == TIM1) {
if (isr) {
furi_assert(api_hal_tim_tim1_isr == NULL);
} else {
furi_assert(api_hal_tim_tim1_isr != NULL);
}
api_hal_tim_tim1_isr = isr;
} else {
furi_check(0);
}
@@ -43,7 +51,7 @@ void api_hal_interrupt_set_dma_channel_isr(DMA_TypeDef* dma, uint32_t channel, A
furi_check(channel < API_HAL_INTERRUPT_DMA_CHANNELS_COUNT);
if (dma == DMA1) {
api_hal_dma_channel_isr[0][channel] = isr;
} else if (dma == DMA1) {
} else if (dma == DMA2) {
api_hal_dma_channel_isr[1][channel] = isr;
} else {
furi_check(0);
@@ -73,6 +81,15 @@ void TIM2_IRQHandler(void) {
}
}
/* Timer 1 Update */
void TIM1_UP_TIM16_IRQHandler(void) {
if (api_hal_tim_tim1_isr) {
api_hal_tim_tim1_isr();
} else {
HAL_TIM_IRQHandler(&htim1);
}
}
/* DMA 1 */
void DMA1_Channel1_IRQHandler(void) {
if (api_hal_dma_channel_isr[0][0]) api_hal_dma_channel_isr[0][0]();

555
firmware/targets/f6/api-hal/api-hal-irda.c
View File

@@ -1,4 +1,8 @@
#include "api-hal-irda.h"
#include "api-hal-delay.h"
#include "furi/check.h"
#include "stm32wbxx_ll_dma.h"
#include "sys/_stdint.h"
#include <cmsis_os2.h>
#include <api-hal-interrupt.h>
#include <api-hal-resources.h>
@@ -9,81 +13,115 @@
#include <stdio.h>
#include <furi.h>
#include <math.h>
#include <main.h>
#include <api-hal-pwm.h>
static struct{
ApiHalIrdaCaptureCallback capture_callback;
#define IRDA_TIM_TX_DMA_BUFFER_SIZE 200
#define IRDA_POLARITY_SHIFT 1
#define IRDA_TX_CCMR_HIGH (TIM_CCMR2_OC3PE | LL_TIM_OCMODE_PWM2) /* Mark time - enable PWM2 mode */
#define IRDA_TX_CCMR_LOW (TIM_CCMR2_OC3PE | LL_TIM_OCMODE_FORCED_INACTIVE) /* Space time - force low */
typedef struct{
ApiHalIrdaRxCaptureCallback capture_callback;
void *capture_context;
ApiHalIrdaTimeoutCallback timeout_callback;
ApiHalIrdaRxTimeoutCallback timeout_callback;
void *timeout_context;
} timer_irda;
} IrdaTimRx;
typedef enum{
TimerIRQSourceCCI1,
TimerIRQSourceCCI2,
} TimerIRQSource;
typedef struct{
uint8_t* polarity;
uint16_t* data;
size_t size;
bool packet_end;
bool last_packet_end;
} IrdaTxBuf;
static void api_hal_irda_handle_timeout(void) {
/* Timers CNT register starts to counting from 0 to ARR, but it is
* reseted when Channel 1 catches interrupt. It is not reseted by
* channel 2, though, so we have to distract it's values (see TimerIRQSourceCCI1 ISR).
* This can cause false timeout: when time is over, but we started
* receiving new signal few microseconds ago, because CNT register
* is reseted once per period, not per sample. */
if (LL_GPIO_IsInputPinSet(gpio_irda_rx.port, gpio_irda_rx.pin) == 0)
return;
typedef struct {
float cycle_duration;
ApiHalIrdaTxGetDataCallback data_callback;
void* data_context;
IrdaTxBuf buffer[2];
osSemaphoreId_t stop_semaphore;
} IrdaTimTx;
if (timer_irda.timeout_callback)
timer_irda.timeout_callback(timer_irda.timeout_context);
}
typedef enum {
IrdaStateIdle, /** Api Hal Irda is ready to start RX or TX */
IrdaStateAsyncRx, /** Async RX started */
IrdaStateAsyncTx, /** Async TX started, DMA and timer is on */
IrdaStateAsyncTxStopReq, /** Async TX started, async stop request received */
IrdaStateAsyncTxStopInProgress, /** Async TX started, stop request is processed and we wait for last data to be sent */
IrdaStateAsyncTxStopped, /** Async TX complete, cleanup needed */
IrdaStateMAX,
} IrdaState;
/* High pin level is a Space state of IRDA signal. Invert level for further processing. */
static void api_hal_irda_handle_capture(TimerIRQSource source) {
uint32_t duration = 0;
bool level = 0;
static volatile IrdaState api_hal_irda_state = IrdaStateIdle;
static IrdaTimTx irda_tim_tx;
static IrdaTimRx irda_tim_rx;
switch (source) {
case TimerIRQSourceCCI1:
duration = LL_TIM_IC_GetCaptureCH1(TIM2) - LL_TIM_IC_GetCaptureCH2(TIM2);
level = 1;
break;
case TimerIRQSourceCCI2:
duration = LL_TIM_IC_GetCaptureCH2(TIM2);
level = 0;
break;
default:
furi_check(0);
}
static bool api_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift);
static void api_hal_irda_async_tx_free_resources(void);
static void api_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift);
static void api_hal_irda_tx_dma_set_buffer(uint8_t buf_num);
static void api_hal_irda_tx_fill_buffer_last(uint8_t buf_num);
static uint8_t api_hal_irda_get_current_dma_tx_buffer(void);
static void api_hal_irda_tx_dma_polarity_isr();
static void api_hal_irda_tx_dma_isr();
if (timer_irda.capture_callback)
timer_irda.capture_callback(timer_irda.capture_context, level, duration);
}
static void api_hal_irda_tim_rx_isr() {
static void api_hal_irda_isr() {
/* Timeout */
if(LL_TIM_IsActiveFlag_CC3(TIM2)) {
LL_TIM_ClearFlag_CC3(TIM2);
api_hal_irda_handle_timeout();
}
if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
LL_TIM_ClearFlag_CC1(TIM2);
furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC1S)) {
// input capture
api_hal_irda_handle_capture(TimerIRQSourceCCI1);
/* Timers CNT register starts to counting from 0 to ARR, but it is
* reseted when Channel 1 catches interrupt. It is not reseted by
* channel 2, though, so we have to distract it's values (see TimerIRQSourceCCI1 ISR).
* This can cause false timeout: when time is over, but we started
* receiving new signal few microseconds ago, because CNT register
* is reseted once per period, not per sample. */
if (LL_GPIO_IsInputPinSet(gpio_irda_rx.port, gpio_irda_rx.pin) != 0) {
if (irda_tim_rx.timeout_callback)
irda_tim_rx.timeout_callback(irda_tim_rx.timeout_context);
}
}
/* Rising Edge */
if(LL_TIM_IsActiveFlag_CC1(TIM2)) {
LL_TIM_ClearFlag_CC1(TIM2);
furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC1S)) {
/* Low pin level is a Mark state of IRDA signal. Invert level for further processing. */
uint32_t duration = LL_TIM_IC_GetCaptureCH1(TIM2) - LL_TIM_IC_GetCaptureCH2(TIM2);
if (irda_tim_rx.capture_callback)
irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 1, duration);
} else {
furi_assert(0);
}
}
/* Falling Edge */
if(LL_TIM_IsActiveFlag_CC2(TIM2)) {
LL_TIM_ClearFlag_CC2(TIM2);
furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
if(READ_BIT(TIM2->CCMR1, TIM_CCMR1_CC2S)) {
// input capture
api_hal_irda_handle_capture(TimerIRQSourceCCI2);
/* High pin level is a Space state of IRDA signal. Invert level for further processing. */
uint32_t duration = LL_TIM_IC_GetCaptureCH2(TIM2);
if (irda_tim_rx.capture_callback)
irda_tim_rx.capture_callback(irda_tim_rx.capture_context, 0, duration);
} else {
furi_assert(0);
}
}
}
void api_hal_irda_rx_irq_init(void) {
void api_hal_irda_async_rx_start(void) {
furi_assert(api_hal_irda_state == IrdaStateIdle);
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
@@ -114,50 +152,433 @@ void api_hal_irda_rx_irq_init(void) {
LL_TIM_IC_SetActiveInput(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ACTIVEINPUT_INDIRECTTI);
LL_TIM_IC_SetPrescaler(TIM2, LL_TIM_CHANNEL_CH2, LL_TIM_ICPSC_DIV1);
api_hal_interrupt_set_timer_isr(TIM2, api_hal_irda_tim_rx_isr);
api_hal_irda_state = IrdaStateAsyncRx;
LL_TIM_EnableIT_CC1(TIM2);
LL_TIM_EnableIT_CC2(TIM2);
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
api_hal_interrupt_set_timer_isr(TIM2, api_hal_irda_isr);
LL_TIM_SetCounter(TIM2, 0);
LL_TIM_EnableCounter(TIM2);
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
NVIC_EnableIRQ(TIM2_IRQn);
}
void api_hal_irda_rx_irq_deinit(void) {
void api_hal_irda_async_rx_stop(void) {
furi_assert(api_hal_irda_state == IrdaStateAsyncRx);
LL_TIM_DeInit(TIM2);
api_hal_interrupt_set_timer_isr(TIM2, NULL);
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2);
api_hal_irda_state = IrdaStateIdle;
}
void api_hal_irda_rx_timeout_irq_init(uint32_t timeout_ms) {
void api_hal_irda_async_rx_set_timeout(uint32_t timeout_ms) {
LL_TIM_OC_SetCompareCH3(TIM2, timeout_ms * 1000);
LL_TIM_OC_SetMode(TIM2, LL_TIM_CHANNEL_CH3, LL_TIM_OCMODE_ACTIVE);
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH3);
LL_TIM_EnableIT_CC3(TIM2);
}
bool api_hal_irda_rx_irq_is_busy(void) {
return (LL_TIM_IsEnabledIT_CC1(TIM2) || LL_TIM_IsEnabledIT_CC2(TIM2));
bool api_hal_irda_is_busy(void) {
return api_hal_irda_state != IrdaStateIdle;
}
void api_hal_irda_rx_irq_set_callback(ApiHalIrdaCaptureCallback callback, void *ctx) {
timer_irda.capture_callback = callback;
timer_irda.capture_context = ctx;
void api_hal_irda_async_rx_set_capture_isr_callback(ApiHalIrdaRxCaptureCallback callback, void *ctx) {
irda_tim_rx.capture_callback = callback;
irda_tim_rx.capture_context = ctx;
}
void api_hal_irda_rx_timeout_irq_set_callback(ApiHalIrdaTimeoutCallback callback, void *ctx) {
timer_irda.timeout_callback = callback;
timer_irda.timeout_context = ctx;
void api_hal_irda_async_rx_set_timeout_isr_callback(ApiHalIrdaRxTimeoutCallback callback, void *ctx) {
irda_tim_rx.timeout_callback = callback;
irda_tim_rx.timeout_context = ctx;
}
void api_hal_irda_pwm_set(float value, float freq) {
hal_pwmn_set(value, freq, &IRDA_TX_TIM, IRDA_TX_CH);
static void api_hal_irda_tx_dma_terminate(void) {
LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_2);
furi_assert(api_hal_irda_state == IrdaStateAsyncTxStopInProgress);
LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
LL_TIM_DisableCounter(TIM1);
osStatus_t status = osSemaphoreRelease(irda_tim_tx.stop_semaphore);
furi_check(status == osOK);
api_hal_irda_state = IrdaStateAsyncTxStopped;
}
void api_hal_irda_pwm_stop() {
hal_pwmn_stop(&IRDA_TX_TIM, IRDA_TX_CH);
static uint8_t api_hal_irda_get_current_dma_tx_buffer(void) {
uint8_t buf_num = 0;
uint32_t buffer_adr = LL_DMA_GetMemoryAddress(DMA1, LL_DMA_CHANNEL_2);
if (buffer_adr == (uint32_t) irda_tim_tx.buffer[0].data) {
buf_num = 0;
} else if (buffer_adr == (uint32_t) irda_tim_tx.buffer[1].data) {
buf_num = 1;
} else {
furi_assert(0);
}
return buf_num;
}
static void api_hal_irda_tx_dma_polarity_isr() {
if (LL_DMA_IsActiveFlag_TE1(DMA1)) {
LL_DMA_ClearFlag_TE1(DMA1);
furi_check(0);
}
if (LL_DMA_IsActiveFlag_TC1(DMA1) && LL_DMA_IsEnabledIT_TC(DMA1, LL_DMA_CHANNEL_1)) {
LL_DMA_ClearFlag_TC1(DMA1);
furi_check((api_hal_irda_state == IrdaStateAsyncTx)
|| (api_hal_irda_state == IrdaStateAsyncTxStopReq)
|| (api_hal_irda_state == IrdaStateAsyncTxStopInProgress));
/* actually TC2 is processed and buffer is next buffer */
uint8_t next_buf_num = api_hal_irda_get_current_dma_tx_buffer();
api_hal_irda_tx_dma_set_polarity(next_buf_num, 0);
}
}
static void api_hal_irda_tx_dma_isr() {
if (LL_DMA_IsActiveFlag_TE2(DMA1)) {
LL_DMA_ClearFlag_TE2(DMA1);
furi_check(0);
}
if (LL_DMA_IsActiveFlag_HT2(DMA1) && LL_DMA_IsEnabledIT_HT(DMA1, LL_DMA_CHANNEL_2)) {
LL_DMA_ClearFlag_HT2(DMA1);
uint8_t buf_num = api_hal_irda_get_current_dma_tx_buffer();
uint8_t next_buf_num = !buf_num;
if (irda_tim_tx.buffer[buf_num].last_packet_end) {
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
} else if (!irda_tim_tx.buffer[buf_num].packet_end || (api_hal_irda_state == IrdaStateAsyncTx)) {
bool result = api_hal_irda_tx_fill_buffer(next_buf_num, 0);
if (irda_tim_tx.buffer[next_buf_num].last_packet_end) {
LL_DMA_DisableIT_HT(DMA1, LL_DMA_CHANNEL_2);
}
if (!result) {
furi_assert(0);
api_hal_irda_state = IrdaStateAsyncTxStopReq;
}
} else if (api_hal_irda_state == IrdaStateAsyncTxStopReq) {
/* fallthrough */
} else {
furi_check(0);
}
}
if (LL_DMA_IsActiveFlag_TC2(DMA1) && LL_DMA_IsEnabledIT_TC(DMA1, LL_DMA_CHANNEL_2)) {
LL_DMA_ClearFlag_TC2(DMA1);
furi_check((api_hal_irda_state == IrdaStateAsyncTxStopInProgress)
|| (api_hal_irda_state == IrdaStateAsyncTxStopReq)
|| (api_hal_irda_state == IrdaStateAsyncTx));
uint8_t buf_num = api_hal_irda_get_current_dma_tx_buffer();
uint8_t next_buf_num = !buf_num;
if (api_hal_irda_state == IrdaStateAsyncTxStopInProgress) {
api_hal_irda_tx_dma_terminate();
} else if (irda_tim_tx.buffer[buf_num].last_packet_end
|| (irda_tim_tx.buffer[buf_num].packet_end && (api_hal_irda_state == IrdaStateAsyncTxStopReq))) {
api_hal_irda_state = IrdaStateAsyncTxStopInProgress;
api_hal_irda_tx_fill_buffer_last(next_buf_num);
api_hal_irda_tx_dma_set_buffer(next_buf_num);
} else {
/* if it's not end of the packet - continue receiving */
api_hal_irda_tx_dma_set_buffer(next_buf_num);
}
}
}
static void api_hal_irda_configure_tim_pwm_tx(uint32_t freq, float duty_cycle)
{
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
/* LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP); */
LL_TIM_DisableCounter(TIM1);
LL_TIM_SetRepetitionCounter(TIM1, 0);
LL_TIM_SetCounter(TIM1, 0);
LL_TIM_SetPrescaler(TIM1, 0);
LL_TIM_SetCounterMode(TIM1, LL_TIM_COUNTERMODE_UP);
LL_TIM_EnableARRPreload(TIM1);
LL_TIM_SetAutoReload(TIM1, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIM1), freq));
LL_TIM_OC_SetCompareCH3(TIM1, ( (LL_TIM_GetAutoReload(TIM1) + 1 ) * (1 - duty_cycle)));
LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH3);
/* LL_TIM_OCMODE_PWM2 set by DMA */
LL_TIM_OC_SetMode(TIM1, LL_TIM_CHANNEL_CH3, LL_TIM_OCMODE_FORCED_INACTIVE);
LL_TIM_OC_SetPolarity(TIM1, LL_TIM_CHANNEL_CH3N, LL_TIM_OCPOLARITY_HIGH);
LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH3);
LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH3N);
LL_TIM_DisableIT_CC3(TIM1);
LL_TIM_DisableMasterSlaveMode(TIM1);
LL_TIM_EnableAllOutputs(TIM1);
LL_TIM_DisableIT_UPDATE(TIM1);
LL_TIM_EnableDMAReq_UPDATE(TIM1);
NVIC_SetPriority(TIM1_UP_TIM16_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
}
static void api_hal_irda_configure_tim_cmgr2_dma_tx(void) {
LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
LL_DMA_InitTypeDef dma_config = {0};
dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->CCMR2);
dma_config.MemoryOrM2MDstAddress = (uint32_t) NULL;
dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
dma_config.Mode = LL_DMA_MODE_NORMAL;
dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
/* fill word to have other bits set to 0 */
dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
dma_config.NbData = 0;
dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM1_UP;
dma_config.Priority = LL_DMA_PRIORITY_VERYHIGH;
LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &dma_config);
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, api_hal_irda_tx_dma_polarity_isr);
LL_DMA_ClearFlag_TE1(DMA1);
LL_DMA_ClearFlag_TC1(DMA1);
LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
}
static void api_hal_irda_configure_tim_rcr_dma_tx(void) {
LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
LL_DMA_InitTypeDef dma_config = {0};
dma_config.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->RCR);
dma_config.MemoryOrM2MDstAddress = (uint32_t) NULL;
dma_config.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
dma_config.Mode = LL_DMA_MODE_NORMAL;
dma_config.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
dma_config.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
dma_config.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
dma_config.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
dma_config.NbData = 0;
dma_config.PeriphRequest = LL_DMAMUX_REQ_TIM1_UP;
dma_config.Priority = LL_DMA_PRIORITY_MEDIUM;
LL_DMA_Init(DMA1, LL_DMA_CHANNEL_2, &dma_config);
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_2, api_hal_irda_tx_dma_isr);
LL_DMA_ClearFlag_TC2(DMA1);
LL_DMA_ClearFlag_HT2(DMA1);
LL_DMA_ClearFlag_TE2(DMA1);
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_2);
LL_DMA_EnableIT_HT(DMA1, LL_DMA_CHANNEL_2);
LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_2);
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
NVIC_EnableIRQ(DMA1_Channel2_IRQn);
}
static void api_hal_irda_tx_fill_buffer_last(uint8_t buf_num) {
furi_assert(buf_num < 2);
furi_assert(api_hal_irda_state != IrdaStateAsyncRx);
furi_assert(api_hal_irda_state < IrdaStateMAX);
furi_assert(irda_tim_tx.data_callback);
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
furi_assert(buffer->data != NULL);
furi_assert(buffer->polarity != NULL);
irda_tim_tx.buffer[buf_num].data[0] = 0; // 1 pulse
irda_tim_tx.buffer[buf_num].polarity[0] = IRDA_TX_CCMR_LOW;
irda_tim_tx.buffer[buf_num].data[1] = 0; // 1 pulse
irda_tim_tx.buffer[buf_num].polarity[1] = IRDA_TX_CCMR_LOW;
irda_tim_tx.buffer[buf_num].size = 2;
irda_tim_tx.buffer[buf_num].last_packet_end = true;
irda_tim_tx.buffer[buf_num].packet_end = true;
}
static bool api_hal_irda_tx_fill_buffer(uint8_t buf_num, uint8_t polarity_shift) {
furi_assert(buf_num < 2);
furi_assert(api_hal_irda_state != IrdaStateAsyncRx);
furi_assert(api_hal_irda_state < IrdaStateMAX);
furi_assert(irda_tim_tx.data_callback);
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
furi_assert(buffer->data != NULL);
furi_assert(buffer->polarity != NULL);
ApiHalIrdaTxGetDataState status = ApiHalIrdaTxGetDataStateOk;
uint32_t duration = 0;
bool level = 0;
size_t *size = &buffer->size;
size_t polarity_counter = 0;
while (polarity_shift--) {
buffer->polarity[polarity_counter++] = IRDA_TX_CCMR_LOW;
}
for (*size = 0; (*size < IRDA_TIM_TX_DMA_BUFFER_SIZE) && (status == ApiHalIrdaTxGetDataStateOk); ++(*size), ++polarity_counter) {
status = irda_tim_tx.data_callback(irda_tim_tx.data_context, &duration, &level);
if (status == ApiHalIrdaTxGetDataStateError) {
furi_assert(0);
break;
}
uint32_t num_of_impulses = roundf(duration / irda_tim_tx.cycle_duration);
if ((buffer->data[*size] + num_of_impulses - 1) > 0xFFFF) {
furi_assert(0);
status = ApiHalIrdaTxGetDataStateError;
break;
}
buffer->polarity[polarity_counter] = level ? IRDA_TX_CCMR_HIGH : IRDA_TX_CCMR_LOW;
buffer->data[*size] = num_of_impulses - 1;
}
buffer->last_packet_end = (status == ApiHalIrdaTxGetDataStateLastDone);
buffer->packet_end = buffer->last_packet_end || (status == ApiHalIrdaTxGetDataStateDone);
return status != ApiHalIrdaTxGetDataStateError;
}
static void api_hal_irda_tx_dma_set_polarity(uint8_t buf_num, uint8_t polarity_shift) {
furi_assert(buf_num < 2);
furi_assert(api_hal_irda_state < IrdaStateMAX);
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
furi_assert(buffer->polarity != NULL);
__disable_irq();
bool channel_enabled = LL_DMA_IsEnabledChannel(DMA1, LL_DMA_CHANNEL_1);
if (channel_enabled) {
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
}
LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_1, (uint32_t) buffer->polarity);
LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, buffer->size + polarity_shift);
if (channel_enabled) {
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
}
__enable_irq();
}
static void api_hal_irda_tx_dma_set_buffer(uint8_t buf_num) {
furi_assert(buf_num < 2);
furi_assert(api_hal_irda_state < IrdaStateMAX);
IrdaTxBuf* buffer = &irda_tim_tx.buffer[buf_num];
furi_assert(buffer->data != NULL);
/* non-circular mode requires disabled channel before setup */
__disable_irq();
bool channel_enabled = LL_DMA_IsEnabledChannel(DMA1, LL_DMA_CHANNEL_2);
if (channel_enabled) {
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
}
LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_2, (uint32_t)buffer->data);
LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_2, buffer->size);
if (channel_enabled) {
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
}
__enable_irq();
}
static void api_hal_irda_async_tx_free_resources(void) {
furi_assert((api_hal_irda_state == IrdaStateIdle) || (api_hal_irda_state == IrdaStateAsyncTxStopped));
osStatus_t status;
hal_gpio_init_ex(&gpio_irda_tx, GpioModeOutputOpenDrain, GpioPullDown, GpioSpeedLow, 0);
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_1, NULL);
api_hal_interrupt_set_dma_channel_isr(DMA1, LL_DMA_CHANNEL_2, NULL);
LL_TIM_DeInit(TIM1);
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1);
LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1);
status = osSemaphoreDelete(irda_tim_tx.stop_semaphore);
furi_check(status == osOK);
free(irda_tim_tx.buffer[0].data);
free(irda_tim_tx.buffer[1].data);
free(irda_tim_tx.buffer[0].polarity);
free(irda_tim_tx.buffer[1].polarity);
irda_tim_tx.buffer[0].data = NULL;
irda_tim_tx.buffer[1].data = NULL;
irda_tim_tx.buffer[0].polarity = NULL;
irda_tim_tx.buffer[1].polarity = NULL;
}
bool api_hal_irda_async_tx_start(uint32_t freq, float duty_cycle) {
if ((duty_cycle > 1) || (duty_cycle < 0) || (freq > 40000) || (freq < 10000) || (irda_tim_tx.data_callback == NULL)) {
furi_assert(0);
return false;
}
furi_assert(api_hal_irda_state == IrdaStateIdle);
furi_assert(irda_tim_tx.buffer[0].data == NULL);
furi_assert(irda_tim_tx.buffer[1].data == NULL);
furi_assert(irda_tim_tx.buffer[0].polarity == NULL);
furi_assert(irda_tim_tx.buffer[1].polarity == NULL);
size_t alloc_size_data = IRDA_TIM_TX_DMA_BUFFER_SIZE * sizeof(uint16_t);
irda_tim_tx.buffer[0].data = furi_alloc(alloc_size_data);
irda_tim_tx.buffer[1].data = furi_alloc(alloc_size_data);
size_t alloc_size_polarity = (IRDA_TIM_TX_DMA_BUFFER_SIZE + IRDA_POLARITY_SHIFT) * sizeof(uint8_t);
irda_tim_tx.buffer[0].polarity = furi_alloc(alloc_size_polarity);
irda_tim_tx.buffer[1].polarity = furi_alloc(alloc_size_polarity);
irda_tim_tx.stop_semaphore = osSemaphoreNew(1, 0, NULL);
irda_tim_tx.cycle_duration = 1000000.0 / freq;
bool result = api_hal_irda_tx_fill_buffer(0, IRDA_POLARITY_SHIFT);
if (result) {
api_hal_irda_configure_tim_pwm_tx(freq, duty_cycle);
api_hal_irda_configure_tim_cmgr2_dma_tx();
api_hal_irda_configure_tim_rcr_dma_tx();
api_hal_irda_tx_dma_set_polarity(0, IRDA_POLARITY_SHIFT);
api_hal_irda_tx_dma_set_buffer(0);
api_hal_irda_state = IrdaStateAsyncTx;
LL_TIM_ClearFlag_UPDATE(TIM1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
delay_us(5);
LL_TIM_GenerateEvent_UPDATE(TIM1); /* DMA -> TIMx_RCR */
delay_us(5);
LL_GPIO_ResetOutputPin(gpio_irda_tx.port, gpio_irda_tx.pin); /* when disable it prevents false pulse */
hal_gpio_init_ex(&gpio_irda_tx, GpioModeAltFunctionPushPull, GpioPullUp, GpioSpeedHigh, GpioAltFn1TIM1);
__disable_irq();
LL_TIM_GenerateEvent_UPDATE(TIM1); /* TIMx_RCR -> Repetition counter */
LL_TIM_EnableCounter(TIM1);
__enable_irq();
} else {
api_hal_irda_async_tx_free_resources();
}
return result;
}
void api_hal_irda_async_tx_wait_termination(void) {
furi_assert(api_hal_irda_state >= IrdaStateAsyncTx);
furi_assert(api_hal_irda_state < IrdaStateMAX);
osStatus_t status;
status = osSemaphoreAcquire(irda_tim_tx.stop_semaphore, osWaitForever);
furi_check(status == osOK);
api_hal_irda_async_tx_free_resources();
api_hal_irda_state = IrdaStateIdle;
}
void api_hal_irda_async_tx_stop(void) {
furi_assert(api_hal_irda_state >= IrdaStateAsyncTx);
furi_assert(api_hal_irda_state < IrdaStateMAX);
__disable_irq();
if (api_hal_irda_state == IrdaStateAsyncTx)
api_hal_irda_state = IrdaStateAsyncTxStopReq;
__enable_irq();
api_hal_irda_async_tx_wait_termination();
}
void api_hal_irda_async_tx_set_data_isr_callback(ApiHalIrdaTxGetDataCallback callback, void* context) {
furi_assert(api_hal_irda_state == IrdaStateIdle);
irda_tim_tx.data_callback = callback;
irda_tim_tx.data_context = context;
}