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[FL-1911] FuriHal: i2c refactoring (#847)

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* Project: fix release build, replace asserts with checks.
* FuriHal: i2c refactoring, new bus access model, flexible bus gpio configuration.
* FuriHal: set i2c pins to high on detach.
* FuriHal: more i2c bus events, put bus under reset when not used, move bus enable/disable routine to bus handler.
* FuriHal: fix i2c deadlock in power api, add external i2c handle.
This commit is contained in:
あく
2021-11-28 21:28:19 +03:00
committed by GitHub
parent 7c0943e736
commit cf591ef7eb
45 changed files with 1685 additions and 781 deletions
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87
lib/drivers/bq25896.c
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@@ -1,7 +1,6 @@
#include "bq25896.h"
#include "bq25896_reg.h"
#include <furi-hal-i2c.h>
#include <stddef.h>
uint8_t bit_reverse(uint8_t b) {
@@ -11,29 +10,17 @@ uint8_t bit_reverse(uint8_t b) {
return b;
}
bool bq25896_read(uint8_t address, uint8_t* data, size_t size) {
bool ret;
with_furi_hal_i2c(
bool, &ret, () {
return furi_hal_i2c_trx(
POWER_I2C, BQ25896_ADDRESS, &address, 1, data, size, BQ25896_I2C_TIMEOUT);
});
return ret;
bool bq25896_read(FuriHalI2cBusHandle* handle, uint8_t address, uint8_t* data, size_t size) {
return furi_hal_i2c_trx(handle, BQ25896_ADDRESS, &address, 1, data, size, BQ25896_I2C_TIMEOUT);
}
bool bq25896_read_reg(uint8_t address, uint8_t* data) {
bq25896_read(address, data, 1);
return true;
bool bq25896_read_reg(FuriHalI2cBusHandle* handle, uint8_t address, uint8_t* data) {
return bq25896_read(handle, address, data, 1);
}
bool bq25896_write_reg(uint8_t address, uint8_t* data) {
bool bq25896_write_reg(FuriHalI2cBusHandle* handle, uint8_t address, uint8_t* data) {
uint8_t buffer[2] = {address, *data};
bool ret;
with_furi_hal_i2c(
bool, &ret, () {
return furi_hal_i2c_tx(POWER_I2C, BQ25896_ADDRESS, buffer, 2, BQ25896_I2C_TIMEOUT);
});
return ret;
return furi_hal_i2c_tx(handle, BQ25896_ADDRESS, buffer, 2, BQ25896_I2C_TIMEOUT);
}
typedef struct {
@@ -62,62 +49,62 @@ typedef struct {
static bq25896_regs_t bq25896_regs;
void bq25896_init() {
void bq25896_init(FuriHalI2cBusHandle* handle) {
bq25896_regs.r14.REG_RST = 1;
bq25896_write_reg(0x14, (uint8_t*)&bq25896_regs.r14);
bq25896_write_reg(handle, 0x14, (uint8_t*)&bq25896_regs.r14);
// Readout all registers
bq25896_read(0x00, (uint8_t*)&bq25896_regs, sizeof(bq25896_regs));
bq25896_read(handle, 0x00, (uint8_t*)&bq25896_regs, sizeof(bq25896_regs));
// Poll ADC forever
bq25896_regs.r02.CONV_START = 1;
bq25896_regs.r02.CONV_RATE = 1;
bq25896_write_reg(0x02, (uint8_t*)&bq25896_regs.r02);
bq25896_write_reg(handle, 0x02, (uint8_t*)&bq25896_regs.r02);
bq25896_regs.r07.WATCHDOG = WatchdogDisable;
bq25896_write_reg(0x07, (uint8_t*)&bq25896_regs.r07);
bq25896_write_reg(handle, 0x07, (uint8_t*)&bq25896_regs.r07);
bq25896_read(0x00, (uint8_t*)&bq25896_regs, sizeof(bq25896_regs));
bq25896_read(handle, 0x00, (uint8_t*)&bq25896_regs, sizeof(bq25896_regs));
}
void bq25896_poweroff() {
void bq25896_poweroff(FuriHalI2cBusHandle* handle) {
bq25896_regs.r09.BATFET_DIS = 1;
bq25896_write_reg(0x09, (uint8_t*)&bq25896_regs.r09);
bq25896_write_reg(handle, 0x09, (uint8_t*)&bq25896_regs.r09);
}
bool bq25896_is_charging() {
bq25896_read(0x00, (uint8_t*)&bq25896_regs, sizeof(bq25896_regs));
bq25896_read_reg(0x0B, (uint8_t*)&bq25896_regs.r0B);
bool bq25896_is_charging(FuriHalI2cBusHandle* handle) {
bq25896_read(handle, 0x00, (uint8_t*)&bq25896_regs, sizeof(bq25896_regs));
bq25896_read_reg(handle, 0x0B, (uint8_t*)&bq25896_regs.r0B);
return bq25896_regs.r0B.CHRG_STAT != ChrgStatNo;
}
void bq25896_enable_charging() {
void bq25896_enable_charging(FuriHalI2cBusHandle* handle) {
bq25896_regs.r03.CHG_CONFIG = 1;
bq25896_write_reg(0x03, (uint8_t*)&bq25896_regs.r03);
bq25896_write_reg(handle, 0x03, (uint8_t*)&bq25896_regs.r03);
}
void bq25896_disable_charging() {
void bq25896_disable_charging(FuriHalI2cBusHandle* handle) {
bq25896_regs.r03.CHG_CONFIG = 0;
bq25896_write_reg(0x03, (uint8_t*)&bq25896_regs.r03);
bq25896_write_reg(handle, 0x03, (uint8_t*)&bq25896_regs.r03);
}
void bq25896_enable_otg() {
void bq25896_enable_otg(FuriHalI2cBusHandle* handle) {
bq25896_regs.r03.OTG_CONFIG = 1;
bq25896_write_reg(0x03, (uint8_t*)&bq25896_regs.r03);
bq25896_write_reg(handle, 0x03, (uint8_t*)&bq25896_regs.r03);
}
void bq25896_disable_otg() {
void bq25896_disable_otg(FuriHalI2cBusHandle* handle) {
bq25896_regs.r03.OTG_CONFIG = 0;
bq25896_write_reg(0x03, (uint8_t*)&bq25896_regs.r03);
bq25896_write_reg(handle, 0x03, (uint8_t*)&bq25896_regs.r03);
}
bool bq25896_is_otg_enabled() {
bq25896_read_reg(0x03, (uint8_t*)&bq25896_regs.r03);
bool bq25896_is_otg_enabled(FuriHalI2cBusHandle* handle) {
bq25896_read_reg(handle, 0x03, (uint8_t*)&bq25896_regs.r03);
return bq25896_regs.r03.OTG_CONFIG;
}
uint16_t bq25896_get_vbus_voltage() {
bq25896_read_reg(0x11, (uint8_t*)&bq25896_regs.r11);
uint16_t bq25896_get_vbus_voltage(FuriHalI2cBusHandle* handle) {
bq25896_read_reg(handle, 0x11, (uint8_t*)&bq25896_regs.r11);
if(bq25896_regs.r11.VBUS_GD) {
return (uint16_t)bq25896_regs.r11.VBUSV * 100 + 2600;
} else {
@@ -125,22 +112,22 @@ uint16_t bq25896_get_vbus_voltage() {
}
}
uint16_t bq25896_get_vsys_voltage() {
bq25896_read_reg(0x0F, (uint8_t*)&bq25896_regs.r0F);
uint16_t bq25896_get_vsys_voltage(FuriHalI2cBusHandle* handle) {
bq25896_read_reg(handle, 0x0F, (uint8_t*)&bq25896_regs.r0F);
return (uint16_t)bq25896_regs.r0F.SYSV * 20 + 2304;
}
uint16_t bq25896_get_vbat_voltage() {
bq25896_read_reg(0x0E, (uint8_t*)&bq25896_regs.r0E);
uint16_t bq25896_get_vbat_voltage(FuriHalI2cBusHandle* handle) {
bq25896_read_reg(handle, 0x0E, (uint8_t*)&bq25896_regs.r0E);
return (uint16_t)bq25896_regs.r0E.BATV * 20 + 2304;
}
uint16_t bq25896_get_vbat_current() {
bq25896_read_reg(0x12, (uint8_t*)&bq25896_regs.r12);
uint16_t bq25896_get_vbat_current(FuriHalI2cBusHandle* handle) {
bq25896_read_reg(handle, 0x12, (uint8_t*)&bq25896_regs.r12);
return (uint16_t)bq25896_regs.r12.ICHGR * 50;
}
uint32_t bq25896_get_ntc_mpct() {
bq25896_read_reg(0x10, (uint8_t*)&bq25896_regs.r10);
uint32_t bq25896_get_ntc_mpct(FuriHalI2cBusHandle* handle) {
bq25896_read_reg(handle, 0x10, (uint8_t*)&bq25896_regs.r10);
return (uint32_t)bq25896_regs.r10.TSPCT * 465 + 21000;
}