<?xml version="1.0" encoding="UTF-8"?>
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Copyright (c) 2020 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32WB55_CM4</name>
<version>1.8</version>
<description>STM32WB55_CM4</description>
<cpu>
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<!--Bus Interface Properties-->
<!--Cortex-M3 is byte addressable-->
<addressUnitBits>8</addressUnitBits>
<!--the maximum data bit width accessible within a single transfer-->
<width>32</width>
<!--Register Default Properties-->
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>DMA1</name>
<description>Direct memory access controller</description>
<groupName>DMA</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA1_Channel1</name>
<description>DMA1 Channel1 global interrupt</description>
<value>11</value>
</interrupt>
<interrupt>
<name>DMA1_Channel2</name>
<description>DMA1 Channel2 global interrupt</description>
<value>12</value>
</interrupt>
<interrupt>
<name>DMA1_Channel3</name>
<description>DMA1 Channel3 interrupt</description>
<value>13</value>
</interrupt>
<interrupt>
<name>DMA1_Channel4</name>
<description>DMA1 Channel4 interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>DMA1_Channel5</name>
<description>DMA1 Channel5 interrupt</description>
<value>15</value>
</interrupt>
<interrupt>
<name>DMA1_Channel6</name>
<description>DMA1 Channel6 interrupt</description>
<value>16</value>
</interrupt>
<interrupt>
<name>DMA1_Channel7</name>
<description>DMA1 Channel 7 interrupt</description>
<value>17</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF7</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF1</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>interrupt flag clear register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF7</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF7</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF7</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF7</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF6</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF6</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF6</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF6</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF5</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF5</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF5</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF5</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF4</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF4</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF4</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF4</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF3</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF3</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF3</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF3</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF2</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF2</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF2</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF2</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF1</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF1</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF1</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF1</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>channel x configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR1</name>
<displayName>CNDTR1</displayName>
<description>channel x number of data register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR1</name>
<displayName>CPAR1</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR1</name>
<displayName>CMAR1</displayName>
<description>channel x memory address register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>channel x configuration register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR2</name>
<displayName>CNDTR2</displayName>
<description>channel x number of data register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR2</name>
<displayName>CPAR2</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR2</name>
<displayName>CMAR2</displayName>
<description>channel x memory address register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>channel x configuration register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR3</name>
<displayName>CNDTR3</displayName>
<description>channel x number of data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR3</name>
<displayName>CPAR3</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR3</name>
<displayName>CMAR3</displayName>
<description>channel x memory address register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>channel x configuration register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR4</name>
<displayName>CNDTR4</displayName>
<description>channel x number of data register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR4</name>
<displayName>CPAR4</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR4</name>
<displayName>CMAR4</displayName>
<description>channel x memory address register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>channel x configuration register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR5</name>
<displayName>CNDTR5</displayName>
<description>channel x number of data register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR5</name>
<displayName>CPAR5</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR5</name>
<displayName>CMAR5</displayName>
<description>channel x memory address register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>channel x configuration register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR6</name>
<displayName>CNDTR6</displayName>
<description>channel x number of data register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR6</name>
<displayName>CPAR6</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR6</name>
<displayName>CMAR6</displayName>
<description>channel x memory address register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR7</name>
<displayName>CCR7</displayName>
<description>channel x configuration register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR7</name>
<displayName>CNDTR7</displayName>
<description>channel x number of data register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR7</name>
<displayName>CPAR7</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR7</name>
<displayName>CMAR7</displayName>
<description>channel x memory address register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA2</name>
<description>Direct memory access controller</description>
<groupName>DMA</groupName>
<baseAddress>0x40020400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA2_CH1</name>
<description>DMA2 channel 1 interrupt</description>
<value>55</value>
</interrupt>
<interrupt>
<name>DMA2_CH2</name>
<description>DMA2 channel 2 interrupt</description>
<value>56</value>
</interrupt>
<interrupt>
<name>DMA2_CH3</name>
<description>DMA2 channel 3 interrupt</description>
<value>57</value>
</interrupt>
<interrupt>
<name>DMA2_CH4</name>
<description>DMA2 channel 4 interrupt</description>
<value>58</value>
</interrupt>
<interrupt>
<name>DMA2_CH5</name>
<description>DMA2 channel 5 interrupt</description>
<value>59</value>
</interrupt>
<interrupt>
<name>DMA2_CH6</name>
<description>DMA2 channel 6 interrupt</description>
<value>60</value>
</interrupt>
<interrupt>
<name>DMA2_CH7</name>
<description>DMA2 channel 7 interrupt</description>
<value>61</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TEIF7</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF7</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF7</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF7</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF6</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF6</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF6</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF6</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF5</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF5</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF5</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF5</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF4</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF4</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF4</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF4</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF3</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF3</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF3</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF3</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF2</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF2</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF2</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF2</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF1</name>
<description>Channel x transfer error flag (x = 1 ..7)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIF1</name>
<description>Channel x half transfer flag (x = 1 ..7)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF1</name>
<description>Channel x transfer complete flag (x = 1 ..7)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GIF1</name>
<description>Channel x global interrupt flag (x = 1 ..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>interrupt flag clear register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTEIF7</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF7</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF7</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF7</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF6</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF6</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF6</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF6</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF5</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF5</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF5</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF5</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF4</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF4</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF4</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF4</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF3</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF3</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF3</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF3</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF2</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF2</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF2</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF2</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF1</name>
<description>Channel x transfer error clear (x = 1 ..7)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHTIF1</name>
<description>Channel x half transfer clear (x = 1 ..7)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF1</name>
<description>Channel x transfer complete clear (x = 1 ..7)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CGIF1</name>
<description>Channel x global interrupt clear (x = 1 ..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>channel x configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR1</name>
<displayName>CNDTR1</displayName>
<description>channel x number of data register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR1</name>
<displayName>CPAR1</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR1</name>
<displayName>CMAR1</displayName>
<description>channel x memory address register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>channel x configuration register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR2</name>
<displayName>CNDTR2</displayName>
<description>channel x number of data register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR2</name>
<displayName>CPAR2</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR2</name>
<displayName>CMAR2</displayName>
<description>channel x memory address register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>channel x configuration register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR3</name>
<displayName>CNDTR3</displayName>
<description>channel x number of data register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR3</name>
<displayName>CPAR3</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR3</name>
<displayName>CMAR3</displayName>
<description>channel x memory address register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>channel x configuration register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR4</name>
<displayName>CNDTR4</displayName>
<description>channel x number of data register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR4</name>
<displayName>CPAR4</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR4</name>
<displayName>CMAR4</displayName>
<description>channel x memory address register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>channel x configuration register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR5</name>
<displayName>CNDTR5</displayName>
<description>channel x number of data register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR5</name>
<displayName>CPAR5</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR5</name>
<displayName>CMAR5</displayName>
<description>channel x memory address register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>channel x configuration register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR6</name>
<displayName>CNDTR6</displayName>
<description>channel x number of data register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR6</name>
<displayName>CPAR6</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR6</name>
<displayName>CMAR6</displayName>
<description>channel x memory address register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR7</name>
<displayName>CCR7</displayName>
<description>channel x configuration register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM2MEM</name>
<description>Memory to memory mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PL</name>
<description>Channel priority level</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MSIZE</name>
<description>Memory size</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Channel enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNDTR7</name>
<displayName>CNDTR7</displayName>
<description>channel x number of data register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data to transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPAR7</name>
<displayName>CPAR7</displayName>
<description>channel x peripheral address register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMAR7</name>
<displayName>CMAR7</displayName>
<description>channel x memory address register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSELR</name>
<displayName>CSELR</displayName>
<description>channel selection register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C7S</name>
<description>DMA channel 7 selection</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C6S</name>
<description>DMA channel 6 selection</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C5S</name>
<description>DMA channel 5 selection</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C4S</name>
<description>DMA channel 4 selection</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C3S</name>
<description>DMA channel 3 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C2S</name>
<description>DMA channel 2 selection</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>C1S</name>
<description>DMA channel 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX1</name>
<description>Direct memory access Multiplexer</description>
<groupName>DMAMUX</groupName>
<baseAddress>0x40020800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMAMUX_OVR</name>
<description>DMAMUX overrun interrupt</description>
<value>62</value>
</interrupt>
<registers>
<register>
<name>C0CR</name>
<displayName>C0CR</displayName>
<description>DMA Multiplexer Channel 0 Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1CR</name>
<displayName>C1CR</displayName>
<description>DMA Multiplexer Channel 1 Control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR</name>
<displayName>C2CR</displayName>
<description>DMA Multiplexer Channel 2 Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C3CR</name>
<displayName>C3CR</displayName>
<description>DMA Multiplexer Channel 3 Control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C4CR</name>
<displayName>C4CR</displayName>
<description>DMA Multiplexer Channel 4 Control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C5CR</name>
<displayName>C5CR</displayName>
<description>DMA Multiplexer Channel 5 Control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C6CR</name>
<displayName>C6CR</displayName>
<description>DMA Multiplexer Channel 6 Control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C7CR</name>
<displayName>C7CR</displayName>
<description>DMA Multiplexer Channel 7 Control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C8CR</name>
<displayName>C8CR</displayName>
<description>DMA Multiplexer Channel 8 Control register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C9CR</name>
<displayName>C9CR</displayName>
<description>DMA Multiplexer Channel 9 Control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C10CR</name>
<displayName>C10CR</displayName>
<description>DMA Multiplexer Channel 10 Control register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C11CR</name>
<displayName>C11CR</displayName>
<description>DMA Multiplexer Channel 11 Control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C12CR</name>
<displayName>C12CR</displayName>
<description>DMA Multiplexer Channel 12 Control register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>C13CR</name>
<displayName>C13CR</displayName>
<description>DMA Multiplexer Channel 13 Control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_ID</name>
<description>SYNC_ID</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>NBREQ</name>
<description>Nb request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPOL</name>
<description>Sync polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EGE</name>
<description>Event Generation Enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOIE</name>
<description>Synchronization Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAREQ_ID</name>
<description>DMA Request ID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>DMA Multiplexer Channel Status register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SOF0</name>
<description>Synchronization Overrun Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF1</name>
<description>Synchronization Overrun Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF2</name>
<description>Synchronization Overrun Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF3</name>
<description>Synchronization Overrun Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF4</name>
<description>Synchronization Overrun Flag 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF5</name>
<description>Synchronization Overrun Flag 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF6</name>
<description>Synchronization Overrun Flag 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF7</name>
<description>Synchronization Overrun Flag 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF8</name>
<description>Synchronization Overrun Flag 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF9</name>
<description>Synchronization Overrun Flag 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF10</name>
<description>Synchronization Overrun Flag 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF11</name>
<description>Synchronization Overrun Flag 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF12</name>
<description>Synchronization Overrun Flag 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOF13</name>
<description>Synchronization Overrun Flag 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>DMA Channel Clear Flag Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSOF0</name>
<description>Synchronization Clear Overrun Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF1</name>
<description>Synchronization Clear Overrun Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF2</name>
<description>Synchronization Clear Overrun Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF3</name>
<description>Synchronization Clear Overrun Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF4</name>
<description>Synchronization Clear Overrun Flag 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF5</name>
<description>Synchronization Clear Overrun Flag 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF6</name>
<description>Synchronization Clear Overrun Flag 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF7</name>
<description>Synchronization Clear Overrun Flag 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF8</name>
<description>Synchronization Clear Overrun Flag 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF9</name>
<description>Synchronization Clear Overrun Flag 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF10</name>
<description>Synchronization Clear Overrun Flag 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF11</name>
<description>Synchronization Clear Overrun Flag 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF12</name>
<description>Synchronization Clear Overrun Flag 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSOF13</name>
<description>Synchronization Clear Overrun Flag 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG0CR</name>
<displayName>RG0CR</displayName>
<description>DMA Request Generator 0 Control Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GNBREQ</name>
<description>Number of Request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>Generation Polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GE</name>
<description>Generation Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_ID</name>
<description>Signal ID</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG1CR</name>
<displayName>RG1CR</displayName>
<description>DMA Request Generator 1 Control Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GNBREQ</name>
<description>Number of Request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>Generation Polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GE</name>
<description>Generation Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_ID</name>
<description>Signal ID</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG2CR</name>
<displayName>RG2CR</displayName>
<description>DMA Request Generator 2 Control Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GNBREQ</name>
<description>Number of Request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>Generation Polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GE</name>
<description>Generation Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_ID</name>
<description>Signal ID</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RG3CR</name>
<displayName>RG3CR</displayName>
<description>DMA Request Generator 3 Control Register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GNBREQ</name>
<description>Number of Request</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>GPOL</name>
<description>Generation Polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GE</name>
<description>Generation Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIE</name>
<description>Overrun Interrupt Enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_ID</name>
<description>Signal ID</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>RGSR</name>
<displayName>RGSR</displayName>
<description>DMA Request Generator Status Register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OF0</name>
<description>Generator Overrun Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OF1</name>
<description>Generator Overrun Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OF2</name>
<description>Generator Overrun Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OF3</name>
<description>Generator Overrun Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RGCFR</name>
<displayName>RGCFR</displayName>
<description>DMA Request Generator Clear Flag Register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COF0</name>
<description>Clear trigger Overrun Flag 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COF1</name>
<description>Clear trigger Overrun Flag 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COF2</name>
<description>Clear trigger Overrun Flag 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COF3</name>
<description>Clear trigger Overrun Flag 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cyclic redundancy check calculation unit</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data register bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>Independent data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR</name>
<description>General-purpose 32-bit data register bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REV_OUT</name>
<description>Reverse output data</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REV_IN</name>
<description>Reverse input data</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>POLYSIZE</name>
<description>Polynomial size</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RESET</name>
<description>RESET bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INIT</name>
<displayName>INIT</displayName>
<description>Initial CRC value</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>CRC_INIT</name>
<description>Programmable initial CRC value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>POL</name>
<displayName>POL</displayName>
<description>polynomial</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x04C11DB7</resetValue>
<fields>
<field>
<name>POL</name>
<description>Programmable polynomial</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LCD</name>
<description>Liquid crystal display controller</description>
<groupName>LCD</groupName>
<baseAddress>0x40002400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LCD</name>
<description>LCD global interrupt</description>
<value>49</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIAS</name>
<description>Bias selector</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DUTY</name>
<description>Duty selection</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>VSEL</name>
<description>Voltage source selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDEN</name>
<description>LCD controller enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEG</name>
<description>Mux segment enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUFEN</name>
<description>Voltage output buffer enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<displayName>FCR</displayName>
<description>frame control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PS</name>
<description>PS 16-bit prescaler</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DIV</name>
<description>DIV clock divider</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BLINK</name>
<description>Blink mode selection</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>BLINKF</name>
<description>Blink frequency selection</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CC</name>
<description>Contrast control</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEAD</name>
<description>Dead time duration</description>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PON</name>
<description>Pulse ON duration</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>UDDIE</name>
<description>Update display done interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFIE</name>
<description>Start of frame interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HD</name>
<description>High drive enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000020</resetValue>
<fields>
<field>
<name>FCRSF</name>
<description>LCD Frame Control Register Synchronization flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDY</name>
<description>Ready flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>UDD</name>
<description>Update Display Done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>UDR</name>
<description>Update display request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOF</name>
<description>Start of frame flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ENS</name>
<description>ENS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CLR</name>
<displayName>CLR</displayName>
<description>clear register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UDDC</name>
<description>Update display done clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFC</name>
<description>Start of frame flag clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM0</name>
<displayName>RAM_COM0</displayName>
<description>display memory</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM1</name>
<displayName>RAM_COM1</displayName>
<description>display memory</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM2</name>
<displayName>RAM_COM2</displayName>
<description>display memory</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM3</name>
<displayName>RAM_COM3</displayName>
<description>display memory</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM4</name>
<displayName>RAM_COM4</displayName>
<description>display memory</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM5</name>
<displayName>RAM_COM5</displayName>
<description>display memory</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM6</name>
<displayName>RAM_COM6</displayName>
<description>display memory</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RAM_COM7</name>
<displayName>RAM_COM7</displayName>
<description>display memory</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>S31</name>
<description>S31</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S30</name>
<description>S30</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S29</name>
<description>S29</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S28</name>
<description>S28</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S27</name>
<description>S27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S26</name>
<description>S26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S25</name>
<description>S25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S24</name>
<description>S24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S23</name>
<description>S23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S22</name>
<description>S22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S21</name>
<description>S21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S20</name>
<description>S20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S19</name>
<description>S19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S18</name>
<description>S18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S17</name>
<description>S17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S16</name>
<description>S16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S15</name>
<description>S15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S14</name>
<description>S14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S13</name>
<description>S13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S12</name>
<description>S12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S11</name>
<description>S11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S10</name>
<description>S10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S09</name>
<description>S09</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S08</name>
<description>S08</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S07</name>
<description>S07</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S06</name>
<description>S06</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S05</name>
<description>S05</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S04</name>
<description>S04</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S03</name>
<description>S03</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S02</name>
<description>S02</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S01</name>
<description>S01</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S00</name>
<description>S00</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TSC</name>
<description>Touch sensing controller</description>
<groupName>TSC</groupName>
<baseAddress>0x40024000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TSC</name>
<description>TSC global interrupt</description>
<value>39</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTPH</name>
<description>Charge transfer pulse high</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CTPL</name>
<description>Charge transfer pulse low</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SSD</name>
<description>Spread spectrum deviation</description>
<bitOffset>17</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>SSE</name>
<description>Spread spectrum enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSPSC</name>
<description>Spread spectrum prescaler</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGPSC</name>
<description>pulse generator prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MCV</name>
<description>Max count value</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IODEF</name>
<description>I/O Default mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCPOL</name>
<description>Synchronization pin polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AM</name>
<description>Acquisition mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start a new acquisition</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSCE</name>
<description>Touch sensing controller enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>interrupt enable register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCEIE</name>
<description>Max count error interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOAIE</name>
<description>End of acquisition interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>interrupt clear register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCEIC</name>
<description>Max count error interrupt clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOAIC</name>
<description>End of acquisition interrupt clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>interrupt status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCEF</name>
<description>Max count error flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOAF</name>
<description>End of acquisition flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOHCR</name>
<displayName>IOHCR</displayName>
<description>I/O hysteresis control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>G7_IO4</name>
<description>G7_IO4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO3</name>
<description>G7_IO3</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO2</name>
<description>G7_IO2</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO1</name>
<description>G7_IO1</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO4</name>
<description>G6_IO4</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO3</name>
<description>G6_IO3</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO2</name>
<description>G6_IO2</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO1</name>
<description>G6_IO1</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO4</name>
<description>G5_IO4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO3</name>
<description>G5_IO3</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO2</name>
<description>G5_IO2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO1</name>
<description>G5_IO1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO4</name>
<description>G4_IO4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO3</name>
<description>G4_IO3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO2</name>
<description>G4_IO2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO1</name>
<description>G4_IO1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO4</name>
<description>G3_IO4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO3</name>
<description>G3_IO3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO2</name>
<description>G3_IO2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO1</name>
<description>G3_IO1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO4</name>
<description>G2_IO4</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO3</name>
<description>G2_IO3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO2</name>
<description>G2_IO2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO1</name>
<description>G2_IO1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO4</name>
<description>G1_IO4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO3</name>
<description>G1_IO3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO2</name>
<description>G1_IO2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO1</name>
<description>G1_IO1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOASCR</name>
<displayName>IOASCR</displayName>
<description>I/O analog switch control register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>G7_IO4</name>
<description>G7_IO4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO3</name>
<description>G7_IO3</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO2</name>
<description>G7_IO2</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO1</name>
<description>G7_IO1</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO4</name>
<description>G6_IO4</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO3</name>
<description>G6_IO3</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO2</name>
<description>G6_IO2</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO1</name>
<description>G6_IO1</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO4</name>
<description>G5_IO4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO3</name>
<description>G5_IO3</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO2</name>
<description>G5_IO2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO1</name>
<description>G5_IO1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO4</name>
<description>G4_IO4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO3</name>
<description>G4_IO3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO2</name>
<description>G4_IO2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO1</name>
<description>G4_IO1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO4</name>
<description>G3_IO4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO3</name>
<description>G3_IO3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO2</name>
<description>G3_IO2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO1</name>
<description>G3_IO1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO4</name>
<description>G2_IO4</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO3</name>
<description>G2_IO3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO2</name>
<description>G2_IO2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO1</name>
<description>G2_IO1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO4</name>
<description>G1_IO4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO3</name>
<description>G1_IO3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO2</name>
<description>G1_IO2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO1</name>
<description>G1_IO1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOSCR</name>
<displayName>IOSCR</displayName>
<description>I/O sampling control register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>G7_IO4</name>
<description>G7_IO4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO3</name>
<description>G7_IO3</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO2</name>
<description>G7_IO2</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO1</name>
<description>G7_IO1</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO4</name>
<description>G6_IO4</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO3</name>
<description>G6_IO3</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO2</name>
<description>G6_IO2</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO1</name>
<description>G6_IO1</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO4</name>
<description>G5_IO4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO3</name>
<description>G5_IO3</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO2</name>
<description>G5_IO2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO1</name>
<description>G5_IO1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO4</name>
<description>G4_IO4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO3</name>
<description>G4_IO3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO2</name>
<description>G4_IO2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO1</name>
<description>G4_IO1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO4</name>
<description>G3_IO4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO3</name>
<description>G3_IO3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO2</name>
<description>G3_IO2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO1</name>
<description>G3_IO1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO4</name>
<description>G2_IO4</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO3</name>
<description>G2_IO3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO2</name>
<description>G2_IO2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO1</name>
<description>G2_IO1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO4</name>
<description>G1_IO4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO3</name>
<description>G1_IO3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO2</name>
<description>G1_IO2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO1</name>
<description>G1_IO1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOCCR</name>
<displayName>IOCCR</displayName>
<description>I/O channel control register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>G7_IO4</name>
<description>G7_IO4</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO3</name>
<description>G7_IO3</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO2</name>
<description>G7_IO2</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G7_IO1</name>
<description>G7_IO1</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO4</name>
<description>G6_IO4</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO3</name>
<description>G6_IO3</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO2</name>
<description>G6_IO2</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G6_IO1</name>
<description>G6_IO1</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO4</name>
<description>G5_IO4</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO3</name>
<description>G5_IO3</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO2</name>
<description>G5_IO2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G5_IO1</name>
<description>G5_IO1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO4</name>
<description>G4_IO4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO3</name>
<description>G4_IO3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO2</name>
<description>G4_IO2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G4_IO1</name>
<description>G4_IO1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO4</name>
<description>G3_IO4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO3</name>
<description>G3_IO3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO2</name>
<description>G3_IO2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G3_IO1</name>
<description>G3_IO1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO4</name>
<description>G2_IO4</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO3</name>
<description>G2_IO3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO2</name>
<description>G2_IO2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G2_IO1</name>
<description>G2_IO1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO4</name>
<description>G1_IO4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO3</name>
<description>G1_IO3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO2</name>
<description>G1_IO2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>G1_IO1</name>
<description>G1_IO1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOGCSR</name>
<displayName>IOGCSR</displayName>
<description>I/O group control status register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>G7S</name>
<description>Analog I/O group x status</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G6S</name>
<description>Analog I/O group x status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G5S</name>
<description>Analog I/O group x status</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G4S</name>
<description>Analog I/O group x status</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G3S</name>
<description>Analog I/O group x status</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G2S</name>
<description>Analog I/O group x status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G1S</name>
<description>Analog I/O group x status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>G7E</name>
<description>Analog I/O group x enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>G6E</name>
<description>Analog I/O group x enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>G5E</name>
<description>Analog I/O group x enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>G4E</name>
<description>Analog I/O group x enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>G3E</name>
<description>Analog I/O group x enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>G2E</name>
<description>Analog I/O group x enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>G1E</name>
<description>Analog I/O group x enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IOG1CR</name>
<displayName>IOG1CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOG2CR</name>
<displayName>IOG2CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOG3CR</name>
<displayName>IOG3CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOG4CR</name>
<displayName>IOG4CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOG5CR</name>
<displayName>IOG5CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOG6CR</name>
<displayName>IOG6CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>IOG7CR</name>
<displayName>IOG7CR</displayName>
<description>I/O group x counter register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IWDG</name>
<description>Independent watchdog</description>
<groupName>IWDG</groupName>
<baseAddress>0x40003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>KR</name>
<displayName>KR</displayName>
<description>Key register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Key value (write only, read 0x0000)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Prescaler register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Prescaler divider</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR</name>
<displayName>RLR</displayName>
<description>Reload register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>RL</name>
<description>Watchdog counter reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WVU</name>
<description>Watchdog counter window value update</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RVU</name>
<description>Watchdog counter reload value update</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVU</name>
<description>Watchdog prescaler value update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WINR</name>
<displayName>WINR</displayName>
<description>Window register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>WIN</name>
<description>Watchdog counter window value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDG</name>
<description>System window watchdog</description>
<groupName>WWDG</groupName>
<baseAddress>0x40002C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WWDG</name>
<description>Window Watchdog interrupt</description>
<value>0</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WDGA</name>
<description>Activation bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T</name>
<description>7-bit counter (MSB to LSB)</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field>
<name>WDGTB</name>
<description>Timer base</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EWI</name>
<description>Early wakeup interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>W</name>
<description>7-bit window value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EWIF</name>
<description>Early wakeup interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter-integrated circuit</description>
<groupName>I2C</groupName>
<baseAddress>0x40005400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1_EV</name>
<description>I2C1 event interrupt</description>
<value>30</value>
</interrupt>
<interrupt>
<name>I2C1_ER</name>
<description>I2C1 error interrupt</description>
<value>31</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PE</name>
<description>Peripheral enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXIE</name>
<description>TX Interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXIE</name>
<description>RX Interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDRIE</name>
<description>Address match interrupt enable (slave only)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKIE</name>
<description>Not acknowledge received interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPIE</name>
<description>STOP detection Interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer Complete interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupts enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DNF</name>
<description>Digital noise filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ANFOFF</name>
<description>Analog noise filter OFF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>DMA transmission requests enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDMAEN</name>
<description>DMA reception requests enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBC</name>
<description>Slave byte control</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOSTRETCH</name>
<description>Clock stretching disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUPEN</name>
<description>Wakeup from STOP enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCEN</name>
<description>General call enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHEN</name>
<description>SMBus Host address enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDEN</name>
<description>SMBus Device Default address enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALERTEN</name>
<description>SMBUS alert enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECEN</name>
<description>PEC enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PECBYTE</name>
<description>Packet error checking byte</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTOEND</name>
<description>Automatic end mode (master mode)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RELOAD</name>
<description>NBYTES reload mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBYTES</name>
<description>Number of bytes</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NACK</name>
<description>NACK generation (slave mode)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>Stop generation (master mode)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start generation</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HEAD10R</name>
<description>10-bit address header only read direction (master receiver mode)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD10</name>
<description>10-bit addressing mode (master mode)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_WRN</name>
<description>Transfer direction (master mode)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SADD</name>
<description>Slave address bit (master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>OAR1</name>
<displayName>OAR1</displayName>
<description>Own address register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA1</name>
<description>Interface address</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>OA1MODE</name>
<description>Own Address 1 10-bit mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OA1EN</name>
<description>Own Address 1 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OAR2</name>
<displayName>OAR2</displayName>
<description>Own address register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OA2</name>
<description>Interface address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>OA2MSK</name>
<description>Own Address 2 masks</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OA2EN</name>
<description>Own Address 2 enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMINGR</name>
<displayName>TIMINGR</displayName>
<description>Timing register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCLL</name>
<description>SCL low period (master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SCLH</name>
<description>SCL high period (master mode)</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SDADEL</name>
<description>Data hold time</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SCLDEL</name>
<description>Data setup time</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Timing prescaler</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEOUTR</name>
<displayName>TIMEOUTR</displayName>
<description>Status register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUTA</name>
<description>Bus timeout A</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TIDLE</name>
<description>Idle clock timeout detection</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTEN</name>
<description>Clock timeout enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMEOUTB</name>
<description>Bus timeout B</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>TEXTEN</name>
<description>Extended clock timeout enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt and Status register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>ADDCODE</name>
<description>Address match code (Slave mode)</description>
<bitOffset>17</bitOffset>
<bitWidth>7</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIR</name>
<description>Transfer direction (Slave mode)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUSY</name>
<description>Bus busy</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALERT</name>
<description>SMBus alert</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout or t_low detection flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PECERR</name>
<description>PEC Error in reception</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR</name>
<description>Overrun/Underrun (slave mode)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ARLO</name>
<description>Arbitration lost</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BERR</name>
<description>Bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCR</name>
<description>Transfer Complete Reload</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TC</name>
<description>Transfer Complete (master mode)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STOPF</name>
<description>Stop detection flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NACKF</name>
<description>Not acknowledge received flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ADDR</name>
<description>Address matched (slave mode)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXNE</name>
<description>Receive data register not empty (receivers)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXIS</name>
<description>Transmit interrupt status (transmitters)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXE</name>
<description>Transmit data register empty (transmitters)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt clear register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALERTCF</name>
<description>Alert flag clear</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUTCF</name>
<description>Timeout detection flag clear</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECCF</name>
<description>PEC Error flag clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRCF</name>
<description>Overrun/Underrun flag clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARLOCF</name>
<description>Arbitration lost flag clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BERRCF</name>
<description>Bus error flag clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOPCF</name>
<description>Stop detection flag clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACKCF</name>
<description>Not Acknowledge flag clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDRCF</name>
<description>Address Matched flag clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PECR</name>
<displayName>PECR</displayName>
<description>PEC register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PEC</name>
<description>Packet error checking register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXDR</name>
<displayName>RXDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDATA</name>
<description>8-bit receive data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXDR</name>
<displayName>TXDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXDATA</name>
<description>8-bit transmit data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C3</name>
<baseAddress>0x40005C00</baseAddress>
<interrupt>
<name>I2C3_EV</name>
<description>I2C3 event interrupt</description>
<value>32</value>
</interrupt>
<interrupt>
<name>I2C3_ER</name>
<description>I2C3 error interrupt</description>
<value>33</value>
</interrupt>
</peripheral>
<peripheral>
<name>Flash</name>
<description>Flash</description>
<groupName>Flash</groupName>
<baseAddress>0x58004000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x90</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<description>Flash global interrupt</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>ACR</name>
<displayName>ACR</displayName>
<description>Access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000600</resetValue>
<fields>
<field>
<name>LATENCY</name>
<description>Latency</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRFTEN</name>
<description>Prefetch enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICEN</name>
<description>Instruction cache enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCEN</name>
<description>Data cache enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICRST</name>
<description>Instruction cache reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DCRST</name>
<description>Data cache reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PES</name>
<description>CPU1 CortexM4 program erase suspend request</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EMPTY</name>
<description>Flash User area empty</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR</name>
<displayName>KEYR</displayName>
<description>Flash key register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEYR</name>
<description>KEYR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTKEYR</name>
<displayName>OPTKEYR</displayName>
<description>Option byte key register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEYR</name>
<description>Option byte key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EOP</name>
<description>End of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OPERR</name>
<description>Operation error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PROGERR</name>
<description>Programming error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WRPERR</name>
<description>Write protected error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGAERR</name>
<description>Programming alignment error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SIZERR</name>
<description>Size error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGSERR</name>
<description>Programming sequence error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MISERR</name>
<description>Fast programming data miss error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FASTERR</name>
<description>Fast programming error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OPTNV</name>
<description>User Option OPTVAL indication</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDERR</name>
<description>PCROP read error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OPTVERR</name>
<description>Option validity error</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CFGBSY</name>
<description>Programming or erase configuration busy</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PESD</name>
<description>Programming or erase operation suspended</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Flash control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xC0000000</resetValue>
<fields>
<field>
<name>PG</name>
<description>Programming</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Page erase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER</name>
<description>This bit triggers the mass erase (all user pages) when set</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PNB</name>
<description>Page number selection</description>
<bitOffset>3</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>STRT</name>
<description>Start</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTSTRT</name>
<description>Options modification start</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTPG</name>
<description>Fast programming</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOPIE</name>
<description>End of operation interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERRIE</name>
<description>PCROP read error interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OBL_LAUNCH</name>
<description>Force the option byte loading</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTLOCK</name>
<description>Options Lock</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>FLASH_CR Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ECCR</name>
<displayName>ECCR</displayName>
<description>Flash ECC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>System Flash ECC fail</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCCIE</name>
<description>ECC correction interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CPUID</name>
<description>CPU identification</description>
<bitOffset>26</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
<description>Flash option register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x10708000</resetValue>
<fields>
<field>
<name>RDP</name>
<description>Read protection level</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESE</name>
<description>Security enabled</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOR_LEV</name>
<description>BOR reset Level</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>nRST_STOP</name>
<description>nRST_STOP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STDBY</name>
<description>nRST_STDBY</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_SHDW</name>
<description>nRST_SHDW</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDWG_SW</name>
<description>Independent watchdog selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWDG_STOP</name>
<description>Independent watchdog counter freeze in Stop mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IWDG_STDBY</name>
<description>Independent watchdog counter freeze in Standby mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDG_SW</name>
<description>Window watchdog selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT1</name>
<description>Boot configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM2_PE</name>
<description>SRAM2 parity check enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM2_RST</name>
<description>SRAM2 Erase when system reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nSWBOOT0</name>
<description>Software Boot0</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nBOOT0</name>
<description>nBoot0 option bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AGC_TRIM</name>
<description>Radio Automatic Gain Control Trimming</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1ASR</name>
<displayName>PCROP1ASR</displayName>
<description>Flash Bank 1 PCROP Start address zone A register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFE00</resetValue>
<fields>
<field>
<name>PCROP1A_STRT</name>
<description>Bank 1 PCROPQ area start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1AER</name>
<displayName>PCROP1AER</displayName>
<description>Flash Bank 1 PCROP End address zone A register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7FFFFE00</resetValue>
<fields>
<field>
<name>PCROP1A_END</name>
<description>Bank 1 PCROP area end offset</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>PCROP_RDP</name>
<description>PCROP area preserved when RDP level decreased</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRP1AR</name>
<displayName>WRP1AR</displayName>
<description>Flash Bank 1 WRP area A address register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFF00FF00</resetValue>
<fields>
<field>
<name>WRP1A_STRT</name>
<description>Bank 1 WRP first area A start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WRP1A_END</name>
<description>Bank 1 WRP first area A end offset</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>WRP1BR</name>
<displayName>WRP1BR</displayName>
<description>Flash Bank 1 WRP area B address register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFF00FF00</resetValue>
<fields>
<field>
<name>WRP1B_STRT</name>
<description>Bank 1 WRP second area B end offset</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WRP1B_END</name>
<description>Bank 1 WRP second area B start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1BSR</name>
<displayName>PCROP1BSR</displayName>
<description>Flash Bank 1 PCROP Start address area B register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFE00</resetValue>
<fields>
<field>
<name>PCROP1B_STRT</name>
<description>Bank 1 PCROP area B start offset</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCROP1BER</name>
<displayName>PCROP1BER</displayName>
<description>Flash Bank 1 PCROP End address area B register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFE00</resetValue>
<fields>
<field>
<name>PCROP1B_END</name>
<description>Bank 1 PCROP area end area B offset</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPCCBR</name>
<displayName>IPCCBR</displayName>
<description>IPCC mailbox data buffer address register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFC000</resetValue>
<fields>
<field>
<name>IPCCDBA</name>
<description>PCC mailbox data buffer base address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2ACR</name>
<displayName>C2ACR</displayName>
<description>CPU2 cortex M0 access control register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000600</resetValue>
<fields>
<field>
<name>PRFTEN</name>
<description>CPU2 cortex M0 prefetch enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICEN</name>
<description>CPU2 cortex M0 instruction cache enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ICRST</name>
<description>CPU2 cortex M0 instruction cache reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PES</name>
<description>CPU2 cortex M0 program erase suspend request</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2SR</name>
<displayName>C2SR</displayName>
<description>CPU2 cortex M0 status register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EOP</name>
<description>End of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPERR</name>
<description>Operation error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PROGERR</name>
<description>Programming error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRPERR</name>
<description>write protection error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGAERR</name>
<description>Programming alignment error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZERR</name>
<description>Size error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PGSERR</name>
<description>Programming sequence error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MISSERR</name>
<description>Fast programming data miss error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTERR</name>
<description>Fast programming error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERR</name>
<description>PCROP read error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CFGBSY</name>
<description>Programming or erase configuration busy</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PESD</name>
<description>Programming or erase operation suspended</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR</name>
<displayName>C2CR</displayName>
<description>CPU2 cortex M0 control register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PG</name>
<description>Programming</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PER</name>
<description>Page erase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MER</name>
<description>Masse erase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PNB</name>
<description>Page Number selection</description>
<bitOffset>3</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>STRT</name>
<description>Start</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSTPG</name>
<description>Fast programming</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOPIE</name>
<description>End of operation interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERRIE</name>
<description>PCROP read error interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SFR</name>
<displayName>SFR</displayName>
<description>Secure flash start address register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFEE00</resetValue>
<fields>
<field>
<name>SFSA</name>
<description>Secure flash start address</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DDS</name>
<description>Disable Cortex M0 debug access</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSD</name>
<description>Flash security disable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRRVR</name>
<displayName>SRRVR</displayName>
<description>Secure SRAM2 start address and cortex M0 reset vector register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x01000000</resetValue>
<fields>
<field>
<name>SBRV</name>
<description>cortex M0 access control register</description>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>SBRSA</name>
<description>Secure backup SRAM2a start address</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>BRSD</name>
<description>backup SRAM2a security disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNBRSA</name>
<description>Secure non backup SRAM2a start address</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>C2OPT</name>
<description>CPU2 cortex M0 boot reset vector memory selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NBRSD</name>
<description>non-backup SRAM2b security disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>QUADSPI</name>
<description>QuadSPI interface</description>
<groupName>QUADSPI</groupName>
<baseAddress>0xA0001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>QUADSPI</name>
<description>QSPI global interrupt</description>
<value>50</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PMM</name>
<description>Polling match mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APMS</name>
<description>Automatic poll mode stop</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOIE</name>
<description>TimeOut interrupt enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMIE</name>
<description>Status match interrupt enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTIE</name>
<description>FIFO threshold interrupt enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTHRES</name>
<description>FIFO threshold level</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SSHIFT</name>
<description>Sample shift</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCEN</name>
<description>Timeout counter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABORT</name>
<description>Abort request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>device configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FSIZE</name>
<description>FLASH memory size</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CSHT</name>
<description>Chip select high time</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CKMODE</name>
<description>Mode 0 / mode 3</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLEVEL</name>
<description>FIFO level</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>Busy</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOF</name>
<description>Timeout flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMF</name>
<description>Status match flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTF</name>
<description>FIFO threshold flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCF</name>
<description>Transfer complete flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEF</name>
<description>Transfer error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<displayName>FCR</displayName>
<description>flag clear register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTOF</name>
<description>Clear timeout flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSMF</name>
<description>Clear status match flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCF</name>
<description>Clear transfer complete flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEF</name>
<description>Clear transfer error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DLR</name>
<displayName>DLR</displayName>
<description>data length register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DL</name>
<description>Data length</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>communication configuration register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DDRM</name>
<description>Double data rate mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIOO</name>
<description>Send instruction only once mode</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FMODE</name>
<description>Functional mode</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMODE</name>
<description>Data mode</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DCYC</name>
<description>Number of dummy cycles</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ABSIZE</name>
<description>Alternate bytes size</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ABMODE</name>
<description>Alternate bytes mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADSIZE</name>
<description>Address size</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADMODE</name>
<description>Address mode</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IMODE</name>
<description>Instruction mode</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INSTRUCTION</name>
<description>Instruction</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>AR</name>
<displayName>AR</displayName>
<description>address register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ABR</name>
<displayName>ABR</displayName>
<description>ABR</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALTERNATE</name>
<description>ALTERNATE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSMKR</name>
<displayName>PSMKR</displayName>
<description>polling status mask register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASK</name>
<description>Status mask</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSMAR</name>
<displayName>PSMAR</displayName>
<description>polling status match register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MATCH</name>
<description>Status match</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PIR</name>
<displayName>PIR</displayName>
<description>polling interval register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTERVAL</name>
<description>Polling interval</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>LPTR</name>
<displayName>LPTR</displayName>
<description>low-power timeout register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUT</name>
<description>Timeout period</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RCC</name>
<description>Reset and clock control</description>
<groupName>RCC</groupName>
<baseAddress>0x58000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RCC</name>
<description>RCC global interrupt</description>
<value>5</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Clock control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000061</resetValue>
<fields>
<field>
<name>PLLSAI1RDY</name>
<description>SAI1 PLL clock ready flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PLLSAI1ON</name>
<description>SAI1 PLL enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLLRDY</name>
<description>Main PLL clock ready flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PLLON</name>
<description>Main PLL enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSEPRE</name>
<description>HSE sysclk and PLL M divider prescaler</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSSON</name>
<description>HSE Clock security system enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>HSEBYP</name>
<description>HSE crystal oscillator bypass</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSERDY</name>
<description>HSE clock ready flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSEON</name>
<description>HSE clock enabled</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSIKERDY</name>
<description>HSI kernel clock ready flag for peripherals requests</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSIASFS</name>
<description>HSI automatic start from Stop</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSIRDY</name>
<description>HSI clock ready flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSIKERON</name>
<description>HSI always enable for peripheral kernels</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSION</name>
<description>HSI clock enabled</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSIRANGE</name>
<description>MSI clock ranges</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSIPLLEN</name>
<description>MSI clock PLL enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSIRDY</name>
<description>MSI clock ready flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MSION</name>
<description>MSI clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ICSCR</name>
<displayName>ICSCR</displayName>
<description>Internal clock sources calibration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x40000000</resetValue>
<fields>
<field>
<name>HSITRIM</name>
<description>HSI clock trimming</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSICAL</name>
<description>HSI clock calibration</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MSITRIM</name>
<description>MSI clock trimming</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MSICAL</name>
<description>MSI clock calibration</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>Clock configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00070000</resetValue>
<fields>
<field>
<name>MCOPRE</name>
<description>Microcontroller clock output prescaler</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MCOSEL</name>
<description>Microcontroller clock output</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PPRE2F</name>
<description>APB2 prescaler flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PPRE1F</name>
<description>APB1 prescaler flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HPREF</name>
<description>AHB prescaler flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STOPWUCK</name>
<description>Wakeup from Stop and CSS backup clock selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PPRE2</name>
<description>APB high-speed prescaler (APB2)</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PPRE1</name>
<description>PB low-speed prescaler (APB1)</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HPRE</name>
<description>AHB prescaler</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SWS</name>
<description>System clock switch status</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SW</name>
<description>System clock switch</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PLLCFGR</name>
<displayName>PLLCFGR</displayName>
<description>PLLSYS configuration register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x22040100</resetValue>
<fields>
<field>
<name>PLLR</name>
<description>Main PLLSYS division factor R for SYSCLK (system clock)</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PLLREN</name>
<description>Main PLLSYSR PLLCLK output enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLQ</name>
<description>Main PLLSYS division factor Q for PLLSYSUSBCLK</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PLLQEN</name>
<description>Main PLLSYSQ output enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLP</name>
<description>Main PLL division factor P for PPLSYSSAICLK</description>
<bitOffset>17</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PLLPEN</name>
<description>Main PLLSYSP output enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLN</name>
<description>Main PLLSYS multiplication factor N</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PLLM</name>
<description>Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PLLSRC</name>
<description>Main PLL, PLLSAI1 and PLLSAI2 entry clock source</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLLSAI1CFGR</name>
<displayName>PLLSAI1CFGR</displayName>
<description>PLLSAI1 configuration register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x22040100</resetValue>
<fields>
<field>
<name>PLLR</name>
<description>PLLSAI division factor R for PLLADC1CLK (ADC clock)</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PLLREN</name>
<description>PLLSAI PLLADC1CLK output enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLQ</name>
<description>SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PLLQEN</name>
<description>SAIPLL PLLSAIUSBCLK output enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLP</name>
<description>SAI1PLL division factor P for PLLSAICLK (SAI1clock)</description>
<bitOffset>17</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>PLLPEN</name>
<description>SAIPLL PLLSAI1CLK output enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLN</name>
<description>SAIPLL multiplication factor for VCO</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIER</name>
<displayName>CIER</displayName>
<description>Clock interrupt enable register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSI2RDYIE</name>
<description>LSI2 ready interrupt enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSI48RDYIE</name>
<description>HSI48 ready interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSECSSIE</name>
<description>LSE clock security system interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLSAI1RDYIE</name>
<description>PLLSAI1 ready interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLRDYIE</name>
<description>PLLSYS ready interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSERDYIE</name>
<description>HSE ready interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSIRDYIE</name>
<description>HSI ready interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIRDYIE</name>
<description>MSI ready interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSERDYIE</name>
<description>LSE ready interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSI1RDYIE</name>
<description>LSI1 ready interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIFR</name>
<displayName>CIFR</displayName>
<description>Clock interrupt flag register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSI2RDYF</name>
<description>LSI2 ready interrupt flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSI48RDYF</name>
<description>HSI48 ready interrupt flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSECSSF</name>
<description>LSE Clock security system interrupt flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSECSSF</name>
<description>HSE Clock security system interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLSAI1RDYF</name>
<description>PLLSAI1 ready interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLRDYF</name>
<description>PLL ready interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSERDYF</name>
<description>HSE ready interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSIRDYF</name>
<description>HSI ready interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIRDYF</name>
<description>MSI ready interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSERDYF</name>
<description>LSE ready interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSI1RDYF</name>
<description>LSI1 ready interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CICR</name>
<displayName>CICR</displayName>
<description>Clock interrupt clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSI2RDYC</name>
<description>LSI2 ready interrupt clear</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSI48RDYC</name>
<description>HSI48 ready interrupt clear</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSECSSC</name>
<description>LSE Clock security system interrupt clear</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSECSSC</name>
<description>HSE Clock security system interrupt clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLSAI1RDYC</name>
<description>PLLSAI1 ready interrupt clear</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLRDYC</name>
<description>PLL ready interrupt clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSERDYC</name>
<description>HSE ready interrupt clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSIRDYC</name>
<description>HSI ready interrupt clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSIRDYC</name>
<description>MSI ready interrupt clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSERDYC</name>
<description>LSE ready interrupt clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSI1RDYC</name>
<description>LSI1 ready interrupt clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPSCR</name>
<displayName>SMPSCR</displayName>
<description>Step Down converter control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000301</resetValue>
<fields>
<field>
<name>SMPSSWS</name>
<description>Step Down converter clock switch status</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SMPSDIV</name>
<description>Step Down converter clock prescaler</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SMPSSEL</name>
<description>Step Down converter clock selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AHB1RSTR</name>
<displayName>AHB1RSTR</displayName>
<description>AHB1 peripheral reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSCRST</name>
<description>Touch Sensing Controller reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCRST</name>
<description>CRC reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAMUXRST</name>
<description>DMAMUX reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2RST</name>
<description>DMA2 reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1RST</name>
<description>DMA1 reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB2RSTR</name>
<displayName>AHB2RSTR</displayName>
<description>AHB2 peripheral reset register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES1RST</name>
<description>AES1 hardware accelerator reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCRST</name>
<description>ADC reset</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOHRST</name>
<description>IO port H reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOERST</name>
<description>IO port E reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIODRST</name>
<description>IO port D reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCRST</name>
<description>IO port C reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBRST</name>
<description>IO port B reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOARST</name>
<description>IO port A reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB3RSTR</name>
<displayName>AHB3RSTR</displayName>
<description>AHB3 peripheral reset register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLASHRST</name>
<description>Flash interface reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPCCRST</name>
<description>IPCC interface reset</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSEMRST</name>
<description>HSEM interface reset</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNGRST</name>
<description>RNG interface reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES2RST</name>
<description>AES2 interface reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PKARST</name>
<description>PKA interface reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QSPIRST</name>
<description>Quad SPI memory interface reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1RSTR1</name>
<displayName>APB1RSTR1</displayName>
<description>APB1 peripheral reset register 1</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LPTIM1RST</name>
<description>Low Power Timer 1 reset</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBFSRST</name>
<description>USB FS reset</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRSRST</name>
<description>CRS reset</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3RST</name>
<description>I2C3 reset</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1RST</name>
<description>I2C1 reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2RST</name>
<description>SPI2 reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDRST</name>
<description>LCD interface reset</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM2RST</name>
<description>TIM2 timer reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1RSTR2</name>
<displayName>APB1RSTR2</displayName>
<description>APB1 peripheral reset register 2</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LPTIM2RST</name>
<description>Low-power timer 2 reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPUART1RST</name>
<description>Low-power UART 1 reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2RSTR</name>
<displayName>APB2RSTR</displayName>
<description>APB2 peripheral reset register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAI1RST</name>
<description>Serial audio interface 1 (SAI1) reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17RST</name>
<description>TIM17 timer reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16RST</name>
<description>TIM16 timer reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1RST</name>
<description>USART1 reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1RST</name>
<description>SPI1 reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM1RST</name>
<description>TIM1 timer reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB3RSTR</name>
<displayName>APB3RSTR</displayName>
<description>APB3 peripheral reset register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFRST</name>
<description>Radio system BLE reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB1ENR</name>
<displayName>AHB1ENR</displayName>
<description>AHB1 peripheral clock enable register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000100</resetValue>
<fields>
<field>
<name>TSCEN</name>
<description>Touch Sensing Controller clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEN</name>
<description>CPU1 CRC clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAMUXEN</name>
<description>DMAMUX clock enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2EN</name>
<description>DMA2 clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1EN</name>
<description>DMA1 clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB2ENR</name>
<displayName>AHB2ENR</displayName>
<description>AHB2 peripheral clock enable register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES1EN</name>
<description>AES1 accelerator clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCEN</name>
<description>ADC clock enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOHEN</name>
<description>IO port H clock enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOEEN</name>
<description>IO port E clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIODEN</name>
<description>IO port D clock enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCEN</name>
<description>IO port C clock enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBEN</name>
<description>IO port B clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOAEN</name>
<description>IO port A clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB3ENR</name>
<displayName>AHB3ENR</displayName>
<description>AHB3 peripheral clock enable register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x02080000</resetValue>
<fields>
<field>
<name>FLASHEN</name>
<description>FLASHEN</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPCCEN</name>
<description>IPCCEN</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSEMEN</name>
<description>HSEMEN</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNGEN</name>
<description>RNGEN</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES2EN</name>
<description>AES2EN</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PKAEN</name>
<description>PKAEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QSPIEN</name>
<description>QSPIEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1ENR1</name>
<displayName>APB1ENR1</displayName>
<description>APB1ENR1</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000400</resetValue>
<fields>
<field>
<name>LPTIM1EN</name>
<description>CPU1 Low power timer 1 clock enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBEN</name>
<description>CPU1 USB clock enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRSEN</name>
<description>CPU1 CRS clock enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3EN</name>
<description>CPU1 I2C3 clock enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1EN</name>
<description>CPU1 I2C1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2EN</name>
<description>CPU1 SPI2 clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDGEN</name>
<description>CPU1 Window watchdog clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCAPBEN</name>
<description>CPU1 RTC APB clock enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDEN</name>
<description>CPU1 LCD clock enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM2EN</name>
<description>CPU1 TIM2 timer clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1ENR2</name>
<displayName>APB1ENR2</displayName>
<description>APB1 peripheral clock enable register 2</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LPTIM2EN</name>
<description>CPU1 LPTIM2EN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPUART1EN</name>
<description>CPU1 Low power UART 1 clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2ENR</name>
<displayName>APB2ENR</displayName>
<description>APB2ENR</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAI1EN</name>
<description>CPU1 SAI1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17EN</name>
<description>CPU1 TIM17 timer clock enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16EN</name>
<description>CPU1 TIM16 timer clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1EN</name>
<description>CPU1 USART1clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1EN</name>
<description>CPU1 SPI1 clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM1EN</name>
<description>CPU1 TIM1 timer clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB1SMENR</name>
<displayName>AHB1SMENR</displayName>
<description>AHB1 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00011207</resetValue>
<fields>
<field>
<name>TSCSMEN</name>
<description>CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCSMEN</name>
<description>CPU1 CRCSMEN</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM1SMEN</name>
<description>CPU1 SRAM1 interface clocks enable during Sleep and Stop modes</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAMUXSMEN</name>
<description>CPU1 DMAMUX clocks enable during Sleep and Stop modes</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2SMEN</name>
<description>CPU1 DMA2 clocks enable during Sleep and Stop modes</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1SMEN</name>
<description>CPU1 DMA1 clocks enable during Sleep and Stop modes</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB2SMENR</name>
<displayName>AHB2SMENR</displayName>
<description>AHB2 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0001209F</resetValue>
<fields>
<field>
<name>AES1SMEN</name>
<description>CPU1 AES1 accelerator clocks enable during Sleep and Stop modes</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCFSSMEN</name>
<description>CPU1 ADC clocks enable during Sleep and Stop modes</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOHSMEN</name>
<description>CPU1 IO port H clocks enable during Sleep and Stop modes</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOESMEN</name>
<description>CPU1 IO port E clocks enable during Sleep and Stop modes</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIODSMEN</name>
<description>CPU1 IO port D clocks enable during Sleep and Stop modes</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCSMEN</name>
<description>CPU1 IO port C clocks enable during Sleep and Stop modes</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBSMEN</name>
<description>CPU1 IO port B clocks enable during Sleep and Stop modes</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOASMEN</name>
<description>CPU1 IO port A clocks enable during Sleep and Stop modes</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB3SMENR</name>
<displayName>AHB3SMENR</displayName>
<description>AHB3 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x03070100</resetValue>
<fields>
<field>
<name>FLASHSMEN</name>
<description>Flash interface clocks enable during CPU1 sleep mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM2SMEN</name>
<description>SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNGSMEN</name>
<description>True RNG clocks enable during CPU1 sleep mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES2SMEN</name>
<description>AES2 accelerator clocks enable during CPU1 sleep mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PKASMEN</name>
<description>PKA accelerator clocks enable during CPU1 sleep mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>QSPISMEN</name>
<description>QSPISMEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1SMENR1</name>
<displayName>APB1SMENR1</displayName>
<description>APB1SMENR1</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x85A04E01</resetValue>
<fields>
<field>
<name>LPTIM1SMEN</name>
<description>Low power timer 1 clocks enable during CPU1 Sleep mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBSMEN</name>
<description>USB FS clocks enable during CPU1 Sleep mode</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRSMEN</name>
<description>CRS clocks enable during CPU1 Sleep mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3SMEN</name>
<description>I2C3 clocks enable during CPU1 Sleep mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1SMEN</name>
<description>I2C1 clocks enable during CPU1 Sleep mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2SMEN</name>
<description>SPI2 clocks enable during CPU1 Sleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WWDGSMEN</name>
<description>Window watchdog clocks enable during CPU1 Sleep mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCAPBSMEN</name>
<description>RTC APB clocks enable during CPU1 Sleep mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDSMEN</name>
<description>LCD clocks enable during CPU1 Sleep mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM2SMEN</name>
<description>TIM2 timer clocks enable during CPU1 Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1SMENR2</name>
<displayName>APB1SMENR2</displayName>
<description>APB1 peripheral clocks enable in Sleep and Stop modes register 2</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000021</resetValue>
<fields>
<field>
<name>LPTIM2SMEN</name>
<description>Low power timer 2 clocks enable during CPU1 Sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPUART1SMEN</name>
<description>Low power UART 1 clocks enable during CPU1 Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2SMENR</name>
<displayName>APB2SMENR</displayName>
<description>APB2SMENR</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00265800</resetValue>
<fields>
<field>
<name>SAI1SMEN</name>
<description>SAI1 clocks enable during CPU1 Sleep mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17SMEN</name>
<description>TIM17 timer clocks enable during CPU1 Sleep mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16SMEN</name>
<description>TIM16 timer clocks enable during CPU1 Sleep mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1SMEN</name>
<description>USART1clocks enable during CPU1 Sleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1SMEN</name>
<description>SPI1 clocks enable during CPU1 Sleep mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM1SMEN</name>
<description>TIM1 timer clocks enable during CPU1 Sleep mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCIPR</name>
<displayName>CCIPR</displayName>
<description>CCIPR</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNGSEL</name>
<description>RNG clock source selection</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADCSEL</name>
<description>ADCs clock source selection</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLK48SEL</name>
<description>48 MHz clock source selection</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAI1SEL</name>
<description>SAI1 clock source selection</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>LPTIM2SEL</name>
<description>Low power timer 2 clock source selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>LPTIM1SEL</name>
<description>Low power timer 1 clock source selection</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2C3SEL</name>
<description>I2C3 clock source selection</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>I2C1SEL</name>
<description>I2C1 clock source selection</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>LPUART1SEL</name>
<description>LPUART1 clock source selection</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>USART1SEL</name>
<description>USART1 clock source selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDCR</name>
<displayName>BDCR</displayName>
<description>BDCR</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSCOSEL</name>
<description>Low speed clock output selection</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSCOEN</name>
<description>Low speed clock output enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BDRST</name>
<description>Backup domain software reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RTCEN</name>
<description>RTC clock enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RTCSEL</name>
<description>RTC clock source selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSECSSD_</name>
<description>CSS on LSE failure detection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LSECSSON</name>
<description>LSECSSON</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSEDRV</name>
<description>SE oscillator drive capability</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSEBYP</name>
<description>LSE oscillator bypass</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSERDY</name>
<description>LSE oscillator ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LSEON</name>
<description>LSE oscillator enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>CSR</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<resetValue>0x0C000000</resetValue>
<fields>
<field>
<name>LPWRRSTF</name>
<description>Low-power reset flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WWDGRSTF</name>
<description>Window watchdog reset flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IWDGRSTF</name>
<description>Independent window watchdog reset flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SFTRSTF</name>
<description>Software reset flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BORRSTF</name>
<description>BOR flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PINRSTF</name>
<description>Pin reset flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OBLRSTF</name>
<description>Option byte loader reset flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RMVF</name>
<description>Remove reset flag</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RFWKPSEL</name>
<description>RF system wakeup clock source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSI2BW</name>
<description>LSI2 oscillator bias configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSI2TRIMOK</name>
<description>LSI2 oscillator trim OK</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LSI2TRIMEN</name>
<description>LSI2 oscillator trimming enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSI2RDY</name>
<description>LSI2 oscillator ready</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LSI2ON</name>
<description>LSI2 oscillator enabled</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSI1RDY</name>
<description>LSI1 oscillator ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LSI1ON</name>
<description>LSI1 oscillator enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RFRSTS</name>
<description>Radio system BLE and 802.15.4 reset status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CRRCR</name>
<displayName>CRRCR</displayName>
<description>Clock recovery RC register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSI48CAL</name>
<description>HSI48 clock calibration</description>
<bitOffset>7</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSI48RDY</name>
<description>HSI48 clock ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSI48ON</name>
<description>HSI48 oscillator enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HSECR</name>
<displayName>HSECR</displayName>
<description>Clock HSE register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<resetValue>0x00000030</resetValue>
<fields>
<field>
<name>HSETUNE</name>
<description>HSE capacitor tuning</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HSEGMC</name>
<description>HSE current control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSES</name>
<description>HSE Sense amplifier threshold</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UNLOCKED</name>
<description>Register lock system</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EXTCFGR</name>
<displayName>EXTCFGR</displayName>
<description>Extended clock recovery register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<resetValue>0x00030000</resetValue>
<fields>
<field>
<name>RFCSS</name>
<description>RF clock source selected</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C2HPREF</name>
<description>CPU2 AHB prescaler flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SHDHPREF</name>
<description>Shared AHB prescaler flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C2HPRE</name>
<description>CPU2 AHB prescaler</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SHDHPRE</name>
<description>Shared AHB prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>C2AHB1ENR</name>
<displayName>C2AHB1ENR</displayName>
<description>CPU2 AHB1 peripheral clock enable register</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSCEN</name>
<description>CPU2 Touch Sensing Controller clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEN</name>
<description>CPU2 CRC clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM1EN</name>
<description>CPU2 SRAM1 clock enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAMUXEN</name>
<description>CPU2 DMAMUX clock enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2EN</name>
<description>CPU2 DMA2 clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1EN</name>
<description>CPU2 DMA1 clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2AHB2ENR</name>
<displayName>C2AHB2ENR</displayName>
<description>CPU2 AHB2 peripheral clock enable register</description>
<addressOffset>0x14C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES1EN</name>
<description>CPU2 AES1 accelerator clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCEN</name>
<description>CPU2 ADC clock enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOHEN</name>
<description>CPU2 IO port H clock enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOEEN</name>
<description>CPU2 IO port E clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIODEN</name>
<description>CPU2 IO port D clock enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCEN</name>
<description>CPU2 IO port C clock enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBEN</name>
<description>CPU2 IO port B clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOAEN</name>
<description>CPU2 IO port A clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2AHB3ENR</name>
<displayName>C2AHB3ENR</displayName>
<description>CPU2 AHB3 peripheral clock enable register</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x02080000</resetValue>
<fields>
<field>
<name>FLASHEN</name>
<description>CPU2 FLASHEN</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IPCCEN</name>
<description>CPU2 IPCCEN</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSEMEN</name>
<description>CPU2 HSEMEN</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNGEN</name>
<description>CPU2 RNGEN</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES2EN</name>
<description>CPU2 AES2EN</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PKAEN</name>
<description>CPU2 PKAEN</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB1ENR1</name>
<displayName>C2APB1ENR1</displayName>
<description>CPU2 APB1ENR1</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000400</resetValue>
<fields>
<field>
<name>LPTIM1EN</name>
<description>CPU2 Low power timer 1 clock enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBEN</name>
<description>CPU2 USB clock enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRSEN</name>
<description>CPU2 CRS clock enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3EN</name>
<description>CPU2 I2C3 clock enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1EN</name>
<description>CPU2 I2C1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2EN</name>
<description>CPU2 SPI2 clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCAPBEN</name>
<description>CPU2 RTC APB clock enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDEN</name>
<description>CPU2 LCD clock enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM2EN</name>
<description>CPU2 TIM2 timer clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB1ENR2</name>
<displayName>C2APB1ENR2</displayName>
<description>CPU2 APB1 peripheral clock enable register 2</description>
<addressOffset>0x15C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LPTIM2EN</name>
<description>CPU2 LPTIM2EN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPUART1EN</name>
<description>CPU2 Low power UART 1 clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB2ENR</name>
<displayName>C2APB2ENR</displayName>
<description>CPU2 APB2ENR</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAI1EN</name>
<description>CPU2 SAI1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17EN</name>
<description>CPU2 TIM17 timer clock enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16EN</name>
<description>CPU2 TIM16 timer clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1EN</name>
<description>CPU2 USART1clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1EN</name>
<description>CPU2 SPI1 clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM1EN</name>
<description>CPU2 TIM1 timer clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB3ENR</name>
<displayName>C2APB3ENR</displayName>
<description>CPU2 APB3ENR</description>
<addressOffset>0x164</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EN802</name>
<description>CPU2 802.15.4 interface clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLEEN</name>
<description>CPU2 BLE interface clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2AHB1SMENR</name>
<displayName>C2AHB1SMENR</displayName>
<description>CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00011207</resetValue>
<fields>
<field>
<name>TSCSMEN</name>
<description>CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCSMEN</name>
<description>CPU2 CRCSMEN</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM1SMEN</name>
<description>SRAM1 interface clock enable during CPU1 CSleep mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAMUXSMEN</name>
<description>CPU2 DMAMUX clocks enable during Sleep and Stop modes</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2SMEN</name>
<description>CPU2 DMA2 clocks enable during Sleep and Stop modes</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1SMEN</name>
<description>CPU2 DMA1 clocks enable during Sleep and Stop modes</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2AHB2SMENR</name>
<displayName>C2AHB2SMENR</displayName>
<description>CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x16C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0001209F</resetValue>
<fields>
<field>
<name>AES1SMEN</name>
<description>CPU2 AES1 accelerator clocks enable during Sleep and Stop modes</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCFSSMEN</name>
<description>CPU2 ADC clocks enable during Sleep and Stop modes</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOHSMEN</name>
<description>CPU2 IO port H clocks enable during Sleep and Stop modes</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOESMEN</name>
<description>CPU2 IO port E clocks enable during Sleep and Stop modes</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIODSMEN</name>
<description>CPU2 IO port D clocks enable during Sleep and Stop modes</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOCSMEN</name>
<description>CPU2 IO port C clocks enable during Sleep and Stop modes</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOBSMEN</name>
<description>CPU2 IO port B clocks enable during Sleep and Stop modes</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIOASMEN</name>
<description>CPU2 IO port A clocks enable during Sleep and Stop modes</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2AHB3SMENR</name>
<displayName>C2AHB3SMENR</displayName>
<description>CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register</description>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x03070000</resetValue>
<fields>
<field>
<name>FLASHSMEN</name>
<description>Flash interface clocks enable during CPU2 sleep modes</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM2SMEN</name>
<description>SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNGSMEN</name>
<description>True RNG clocks enable during CPU2 sleep modes</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES2SMEN</name>
<description>AES2 accelerator clocks enable during CPU2 sleep modes</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PKASMEN</name>
<description>PKA accelerator clocks enable during CPU2 sleep modes</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB1SMENR1</name>
<displayName>C2APB1SMENR1</displayName>
<description>CPU2 APB1SMENR1</description>
<addressOffset>0x178</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x85A04601</resetValue>
<fields>
<field>
<name>LPTIM1SMEN</name>
<description>Low power timer 1 clocks enable during CPU2 Sleep mode</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USBSMEN</name>
<description>USB FS clocks enable during CPU2 Sleep mode</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRSMEN</name>
<description>CRS clocks enable during CPU2 Sleep mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C3SMEN</name>
<description>I2C3 clocks enable during CPU2 Sleep mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1SMEN</name>
<description>I2C1 clocks enable during CPU2 Sleep mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2SMEN</name>
<description>SPI2 clocks enable during CPU2 Sleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCAPBSMEN</name>
<description>RTC APB clocks enable during CPU2 Sleep mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDSMEN</name>
<description>LCD clocks enable during CPU2 Sleep mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM2SMEN</name>
<description>TIM2 timer clocks enable during CPU2 Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB1SMENR2</name>
<displayName>C2APB1SMENR2</displayName>
<description>CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2</description>
<addressOffset>0x17C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000021</resetValue>
<fields>
<field>
<name>LPTIM2SMEN</name>
<description>Low power timer 2 clocks enable during CPU2 Sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPUART1SMEN</name>
<description>Low power UART 1 clocks enable during CPU2 Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB2SMENR</name>
<displayName>C2APB2SMENR</displayName>
<description>CPU2 APB2SMENR</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00265800</resetValue>
<fields>
<field>
<name>SAI1SMEN</name>
<description>SAI1 clocks enable during CPU2 Sleep mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17SMEN</name>
<description>TIM17 timer clocks enable during CPU2 Sleep mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16SMEN</name>
<description>TIM16 timer clocks enable during CPU2 Sleep mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USART1SMEN</name>
<description>USART1clocks enable during CPU2 Sleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI1SMEN</name>
<description>SPI1 clocks enable during CPU2 Sleep mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM1SMEN</name>
<description>TIM1 timer clocks enable during CPU2 Sleep mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB3SMENR</name>
<displayName>C2APB3SMENR</displayName>
<description>CPU2 APB3SMENR</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000003</resetValue>
<fields>
<field>
<name>SMEN802</name>
<description>802.15.4 interface clocks enable during CPU2 Sleep modes</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLESMEN</name>
<description>BLE interface clocks enable during CPU2 Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWR</name>
<description>Power control</description>
<groupName>PWR</groupName>
<baseAddress>0x58000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PWR_SOTF</name>
<description>PWR switching on the fly
interrupt</description>
<value>43</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Power control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>LPR</name>
<description>Low-power run</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VOS</name>
<description>Voltage scaling range selection</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DBP</name>
<description>Disable backup domain write protection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPDS</name>
<description>Flash power down mode during LPsSleep for CPU1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPDR</name>
<description>Flash power down mode during LPRun for CPU1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPMS</name>
<description>Low-power mode selection for CPU1</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Power control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USV</name>
<description>VDDUSB USB supply valid</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVME3</name>
<description>Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVME1</name>
<description>Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLS</name>
<description>Power voltage detector level selection</description>
<bitOffset>1</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PVDE</name>
<description>Power voltage detector enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Power control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00008000</resetValue>
<fields>
<field>
<name>EIWUL</name>
<description>Enable internal wakeup line for CPU1</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EC2H</name>
<description>Enable CPU2 Hold interrupt for CPU1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>E802A</name>
<description>Enable end of activity interrupt for CPU1</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EBLEA</name>
<description>Enable BLE end of activity interrupt for CPU1</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECRPE</name>
<description>Enable critical radio phase end of activity interrupt for CPU1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APC</name>
<description>Apply pull-up and pull-down configuration</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RRS</name>
<description>SRAM2a retention in Standby mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EBORHSDFB</name>
<description>Enable BORH and Step Down counverter forced in Bypass interrups for CPU1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP5</name>
<description>Enable Wakeup pin WKUP5</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP4</name>
<description>Enable Wakeup pin WKUP4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP3</name>
<description>Enable Wakeup pin WKUP3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP2</name>
<description>Enable Wakeup pin WKUP2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP1</name>
<description>Enable Wakeup pin WKUP1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR4</name>
<displayName>CR4</displayName>
<description>Power control register 4</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2BOOT</name>
<description>BOOT CPU2 after reset or wakeup from Stop or Standby modes</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBRS</name>
<description>VBAT battery charging resistor selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBE</name>
<description>VBAT battery charging enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WP5</name>
<description>Wakeup pin WKUP5 polarity</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WP4</name>
<description>Wakeup pin WKUP4 polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WP3</name>
<description>Wakeup pin WKUP3 polarity</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WP2</name>
<description>Wakeup pin WKUP2 polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WP1</name>
<description>Wakeup pin WKUP1 polarity</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR1</name>
<displayName>SR1</displayName>
<description>Power status register 1</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUFI</name>
<description>Internal Wakeup interrupt flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C2HF</name>
<description>CPU2 Hold interrupt flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AF802</name>
<description>802.15.4 end of activity interrupt flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLEAF</name>
<description>BLE end of activity interrupt flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRPEF</name>
<description>Enable critical radio phase end of activity interrupt flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF802</name>
<description>802.15.4 wakeup interrupt flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLEWUF</name>
<description>BLE wakeup interrupt flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BORHF</name>
<description>BORH interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDFBF</name>
<description>Step Down converter forced in Bypass interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF5</name>
<description>Wakeup flag 5</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF4</name>
<description>Wakeup flag 4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF3</name>
<description>Wakeup flag 3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF2</name>
<description>Wakeup flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF1</name>
<description>Wakeup flag 1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR2</name>
<displayName>SR2</displayName>
<description>Power status register 2</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>PVMO3</name>
<description>Peripheral voltage monitoring output: VDDA vs. 1.62 V</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVMO1</name>
<description>Peripheral voltage monitoring output: VDDUSB vs. 1.2 V</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVDO</name>
<description>Power voltage detector output</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VOSF</name>
<description>Voltage scaling flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REGLPF</name>
<description>Low-power regulator flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REGLPS</name>
<description>Low-power regulator started</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDSMPSF</name>
<description>Step Down converter SMPS mode flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDBF</name>
<description>Step Down converter Bypass mode flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>Power status clear register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC2HF</name>
<description>Clear CPU2 Hold interrupt flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C802AF</name>
<description>Clear 802.15.4 end of activity interrupt flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBLEAF</name>
<description>Clear BLE end of activity interrupt flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCRPEF</name>
<description>Clear critical radio phase end of activity interrupt flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C802WUF</name>
<description>Clear 802.15.4 wakeup interrupt flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBLEWUF</name>
<description>Clear BLE wakeup interrupt flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBORHF</name>
<description>Clear BORH interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSMPSFBF</name>
<description>Clear SMPS Step Down converter forced in Bypass interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF5</name>
<description>Clear wakeup flag 5</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF4</name>
<description>Clear wakeup flag 4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF3</name>
<description>Clear wakeup flag 3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF2</name>
<description>Clear wakeup flag 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF1</name>
<description>Clear wakeup flag 1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR5</name>
<displayName>CR5</displayName>
<description>Power control register 5</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00004270</resetValue>
<fields>
<field>
<name>SDEB</name>
<description>Enable Step Down converter SMPS mode enabled</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDBEN</name>
<description>Enable Step Down converter Bypass mode enabled</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMPSCFG</name>
<description>VOS configuration selection (non user)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BORHC</name>
<description>BORH configuration selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDSC</name>
<description>Step Down converter supplt startup current selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDVOS</name>
<description>Step Down converter voltage output scaling</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUCRA</name>
<displayName>PUCRA</displayName>
<description>Power Port A pull-up control register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PU15</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU13</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU12</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU11</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU10</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU9</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU8</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU7</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU6</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU5</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU4</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU3</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU2</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU1</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU0</name>
<description>Port A pull-up bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDCRA</name>
<displayName>PDCRA</displayName>
<description>Power Port A pull-down control register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD14</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD12</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD11</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD10</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD9</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD8</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD7</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD6</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD5</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD4</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD3</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD2</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD1</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD0</name>
<description>Port A pull-down bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUCRB</name>
<displayName>PUCRB</displayName>
<description>Power Port B pull-up control register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PU15</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU14</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU13</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU12</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU11</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU10</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU9</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU8</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU7</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU6</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU5</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU4</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU3</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU2</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU1</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU0</name>
<description>Port B pull-up bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDCRB</name>
<displayName>PDCRB</displayName>
<description>Power Port B pull-down control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD15</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD14</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD13</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD12</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD11</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD10</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD9</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD8</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD7</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD6</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD5</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD3</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD2</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD1</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD0</name>
<description>Port B pull-down bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUCRC</name>
<displayName>PUCRC</displayName>
<description>Power Port C pull-up control register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PU15</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU14</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU13</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU12</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU11</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU10</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU9</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU8</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU7</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU6</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU5</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU4</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU3</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU2</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU1</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU0</name>
<description>Port C pull-up bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDCRC</name>
<displayName>PDCRC</displayName>
<description>Power Port C pull-down control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD15</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD14</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD13</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD12</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD11</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD10</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD9</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD8</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD7</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD6</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD5</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD4</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD3</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD2</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD1</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD0</name>
<description>Port C pull-down bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUCRD</name>
<displayName>PUCRD</displayName>
<description>Power Port D pull-up control register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PU15</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU14</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU13</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU12</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU11</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU10</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU9</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU8</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU7</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU6</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU5</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU4</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU3</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU2</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU1</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU0</name>
<description>Port D pull-up bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDCRD</name>
<displayName>PDCRD</displayName>
<description>Power Port D pull-down control register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD15</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD14</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD13</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD12</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD11</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD10</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD9</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD8</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD7</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD6</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD5</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD4</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD3</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD2</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD1</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD0</name>
<description>Port D pull-down bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUCRE</name>
<displayName>PUCRE</displayName>
<description>Power Port E pull-up control register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PU4</name>
<description>Port E pull-up bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU3</name>
<description>Port E pull-up bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU2</name>
<description>Port E pull-up bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU1</name>
<description>Port E pull-up bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU0</name>
<description>Port E pull-up bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDCRE</name>
<displayName>PDCRE</displayName>
<description>Power Port E pull-down control register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD4</name>
<description>Port E pull-down bit y (y=0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD3</name>
<description>Port E pull-down bit y (y=0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD2</name>
<description>Port E pull-down bit y (y=0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD1</name>
<description>Port E pull-down bit y (y=0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD0</name>
<description>Port E pull-down bit y (y=0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUCRH</name>
<displayName>PUCRH</displayName>
<description>Power Port H pull-up control register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PU3</name>
<description>Port H pull-up bit y (y=0..1)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU1</name>
<description>Port H pull-up bit y (y=0..1)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PU0</name>
<description>Port H pull-up bit y (y=0..1)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDCRH</name>
<displayName>PDCRH</displayName>
<description>Power Port H pull-down control register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD3</name>
<description>Port H pull-down bit y (y=0..1)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD1</name>
<description>Port H pull-down bit y (y=0..1)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PD0</name>
<description>Port H pull-down bit y (y=0..1)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR1</name>
<displayName>C2CR1</displayName>
<description>CPU2 Power control register 1</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EWKUP802</name>
<description>802.15.4 external wakeup signal</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BLEEWKUP</name>
<description>BLE external wakeup signal</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPDS</name>
<description>Flash power down mode during LPSleep for CPU2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPDR</name>
<description>Flash power down mode during LPRun for CPU2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPMS</name>
<description>Low-power mode selection for CPU2</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR3</name>
<displayName>C2CR3</displayName>
<description>CPU2 Power control register 3</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00008000</resetValue>
<fields>
<field>
<name>EIWUL</name>
<description>Enable internal wakeup line for CPU2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APC</name>
<description>Apply pull-up and pull-down configuration for CPU2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>E802WUP</name>
<description>Enable 802.15.4 host wakeup interrupt for CPU2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EBLEWUP</name>
<description>Enable BLE host wakeup interrupt for CPU2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP5</name>
<description>Enable Wakeup pin WKUP5 for CPU2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP4</name>
<description>Enable Wakeup pin WKUP4 for CPU2</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP3</name>
<description>Enable Wakeup pin WKUP3 for CPU2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP2</name>
<description>Enable Wakeup pin WKUP2 for CPU2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EWUP1</name>
<description>Enable Wakeup pin WKUP1 for CPU2</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTSCR</name>
<displayName>EXTSCR</displayName>
<description>Power status clear register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>C2DS</name>
<description>CPU2 deepsleep mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C1DS</name>
<description>CPU1 deepsleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CRPF</name>
<description>Critical Radio system phase</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C2STOPF</name>
<description>System Stop flag for CPU2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C2SBF</name>
<description>System Standby flag for CPU2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C1STOPF</name>
<description>System Stop flag for CPU1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>C1SBF</name>
<description>System Standby flag for CPU1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CCRPF</name>
<description>Clear Critical Radio system phase</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>C2CSSF</name>
<description>Clear CPU2 Stop Standby flags</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>C1CSSF</name>
<description>Clear CPU1 Stop Standby flags</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCFG_VREFBUF</name>
<description>SYSCFG_VREFBUF</description>
<groupName>SYSCFG_VREFBUF</groupName>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x200</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYSCFG_MEMRMP</name>
<displayName>SYSCFG_MEMRMP</displayName>
<description>memory remap register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_MODE</name>
<description>Memory mapping selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_CFGR1</name>
<displayName>SYSCFG_CFGR1</displayName>
<description>configuration register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7C000001</resetValue>
<fields>
<field>
<name>FPU_IE</name>
<description>Floating Point Unit interrupts enable bits</description>
<bitOffset>26</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>I2C3_FMP</name>
<description>I2C3 Fast-mode Plus driving capability activation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1_FMP</name>
<description>I2C1 Fast-mode Plus driving capability activation</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB9_FMP</name>
<description>Fast-mode Plus (Fm+) driving capability activation on PB9</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB8_FMP</name>
<description>Fast-mode Plus (Fm+) driving capability activation on PB8</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB7_FMP</name>
<description>Fast-mode Plus (Fm+) driving capability activation on PB7</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_PB6_FMP</name>
<description>Fast-mode Plus (Fm+) driving capability activation on PB6</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOOSTEN</name>
<description>I/O analog switch voltage booster enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_EXTICR1</name>
<displayName>SYSCFG_EXTICR1</displayName>
<description>external interrupt configuration register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI3</name>
<description>EXTI 3 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI2</name>
<description>EXTI 2 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI1</name>
<description>EXTI 1 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI0</name>
<description>EXTI 0 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_EXTICR2</name>
<displayName>SYSCFG_EXTICR2</displayName>
<description>external interrupt configuration register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI7</name>
<description>EXTI 7 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI6</name>
<description>EXTI 6 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI5</name>
<description>EXTI 5 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI4</name>
<description>EXTI 4 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_EXTICR3</name>
<displayName>SYSCFG_EXTICR3</displayName>
<description>external interrupt configuration register 3</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI11</name>
<description>EXTI 11 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI10</name>
<description>EXTI 10 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI9</name>
<description>EXTI 9 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI8</name>
<description>EXTI 8 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_EXTICR4</name>
<displayName>SYSCFG_EXTICR4</displayName>
<description>external interrupt configuration register 4</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTI15</name>
<description>EXTI15 configuration bits</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI14</name>
<description>EXTI14 configuration bits</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI13</name>
<description>EXTI13 configuration bits</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>EXTI12</name>
<description>EXTI12 configuration bits</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_SCSR</name>
<displayName>SYSCFG_SCSR</displayName>
<description>SCSR</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRAM2BSY</name>
<description>SRAM2 busy by erase operation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRAM2ER</name>
<description>SRAM2 Erase</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>C2RFD</name>
<description>CPU2 SRAM fetch (execution) disable.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SYSCFG_CFGR2</name>
<displayName>SYSCFG_CFGR2</displayName>
<description>CFGR2</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPF</name>
<description>SRAM2 parity error flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCL</name>
<description>ECC Lock</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PVDL</name>
<description>PVD lock enable bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SPL</name>
<description>SRAM2 parity lock bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CLL</name>
<description>Cortex-M4 LOCKUP (Hardfault) output enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>SYSCFG_SWPR</name>
<displayName>SYSCFG_SWPR</displayName>
<description>SRAM2 write protection register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>P31WP</name>
<description>SRAM2 page 31 write protection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P30WP</name>
<description>P30WP</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P29WP</name>
<description>P29WP</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P28WP</name>
<description>P28WP</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P27WP</name>
<description>P27WP</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P26WP</name>
<description>P26WP</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P25WP</name>
<description>P25WP</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P24WP</name>
<description>P24WP</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P23WP</name>
<description>P23WP</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P22WP</name>
<description>P22WP</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P21WP</name>
<description>P21WP</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P20WP</name>
<description>P20WP</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P19WP</name>
<description>P19WP</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P18WP</name>
<description>P18WP</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P17WP</name>
<description>P17WP</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P16WP</name>
<description>P16WP</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P15WP</name>
<description>P15WP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P14WP</name>
<description>P14WP</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P13WP</name>
<description>P13WP</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P12WP</name>
<description>P12WP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P11WP</name>
<description>P11WP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P10WP</name>
<description>P10WP</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P9WP</name>
<description>P9WP</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P8WP</name>
<description>P8WP</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P7WP</name>
<description>P7WP</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P6WP</name>
<description>P6WP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P5WP</name>
<description>P5WP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P4WP</name>
<description>P4WP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P3WP</name>
<description>P3WP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P2WP</name>
<description>P2WP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P1WP</name>
<description>P1WP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P0WP</name>
<description>P0WP</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_SKR</name>
<displayName>SYSCFG_SKR</displayName>
<description>SKR</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>SRAM2 write protection key for software erase</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_SWPR2</name>
<displayName>SYSCFG_SWPR2</displayName>
<description>SRAM2 write protection register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>P63WP</name>
<description>SRAM2 page 63 write protection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P62WP</name>
<description>P62WP</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P61WP</name>
<description>P61WP</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P60WP</name>
<description>P60WP</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P59WP</name>
<description>P59WP</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P58WP</name>
<description>P58WP</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P57WP</name>
<description>P57WP</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P56WP</name>
<description>P56WP</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P55WP</name>
<description>P55WP</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P54WP</name>
<description>P54WP</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P53WP</name>
<description>P53WP</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P52WP</name>
<description>P52WP</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P51WP</name>
<description>P51WP</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P50WP</name>
<description>P50WP</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P49WP</name>
<description>P49WP</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P48WP</name>
<description>P48WP</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P47WP</name>
<description>P47WP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P46WP</name>
<description>P46WP</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P45WP</name>
<description>P45WP</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P44WP</name>
<description>P44WP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P43WP</name>
<description>P43WP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P42WP</name>
<description>P42WP</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P41WP</name>
<description>P41WP</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P40WP</name>
<description>P40WP</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P39WP</name>
<description>P39WP</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P38WP</name>
<description>P38WP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P37WP</name>
<description>P37WP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P36WP</name>
<description>P36WP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P35WP</name>
<description>P35WP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P34WP</name>
<description>P34WP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P33WP</name>
<description>P33WP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>P32WP</name>
<description>P32WP</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VREFBUF_CSR</name>
<displayName>VREFBUF_CSR</displayName>
<description>VREF control and status register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>ENVR</name>
<description>Voltage reference buffer enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HIZ</name>
<description>High impedance mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRS</name>
<description>Voltage reference scale</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VRR</name>
<description>Voltage reference buffer ready</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>VREFBUF_CCR</name>
<displayName>VREFBUF_CCR</displayName>
<description>calibration control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRIM</name>
<description>Trimming code</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_IMR1</name>
<displayName>SYSCFG_IMR1</displayName>
<description>CPU1 interrupt mask register 1</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM1IM</name>
<description>Peripheral TIM1 interrupt mask to CPU1</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM16IM</name>
<description>Peripheral TIM16 interrupt mask to CPU1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIM17IM</name>
<description>Peripheral TIM17 interrupt mask to CPU1</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT5IM</name>
<description>Peripheral EXIT5 interrupt mask to CPU1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT6IM</name>
<description>Peripheral EXIT6 interrupt mask to CPU1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT7IM</name>
<description>Peripheral EXIT7 interrupt mask to CPU1</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT8IM</name>
<description>Peripheral EXIT8 interrupt mask to CPU1</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT9IM</name>
<description>Peripheral EXIT9 interrupt mask to CPU1</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT10IM</name>
<description>Peripheral EXIT10 interrupt mask to CPU1</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT11IM</name>
<description>Peripheral EXIT11 interrupt mask to CPU1</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT12IM</name>
<description>Peripheral EXIT12 interrupt mask to CPU1</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT13IM</name>
<description>Peripheral EXIT13 interrupt mask to CPU1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT14IM</name>
<description>Peripheral EXIT14 interrupt mask to CPU1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXIT15IM</name>
<description>Peripheral EXIT15 interrupt mask to CPU1</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_IMR2</name>
<displayName>SYSCFG_IMR2</displayName>
<description>CPU1 interrupt mask register 2</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PVM3IM</name>
<description>Peripheral PVM3 interrupt mask to CPU1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVM1IM</name>
<description>Peripheral PVM1 interrupt mask to CPU1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVDIM</name>
<description>Peripheral PVD interrupt mask to CPU1</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_C2IMR1</name>
<displayName>SYSCFG_C2IMR1</displayName>
<description>CPU2 interrupt mask register 1</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RTCSTAMP</name>
<description>Peripheral RTCSTAMP interrupt mask to CPU2</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCWKUP</name>
<description>Peripheral RTCWKUP interrupt mask to CPU2</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTCALARM</name>
<description>Peripheral RTCALARM interrupt mask to CPU2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RCC</name>
<description>Peripheral RCC interrupt mask to CPU2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH</name>
<description>Peripheral FLASH interrupt mask to CPU2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PKA</name>
<description>Peripheral PKA interrupt mask to CPU2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RNG</name>
<description>Peripheral RNG interrupt mask to CPU2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES1</name>
<description>Peripheral AES1 interrupt mask to CPU2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMP</name>
<description>Peripheral COMP interrupt mask to CPU2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC</name>
<description>Peripheral ADC interrupt mask to CPU2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_C2IMR2</name>
<displayName>SYSCFG_C2IMR2</displayName>
<description>CPU2 interrupt mask register 1</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA1_CH1_IM</name>
<description>Peripheral DMA1 CH1 interrupt mask to CPU2</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1_CH2_IM</name>
<description>Peripheral DMA1 CH2 interrupt mask to CPU2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1_CH3_IM</name>
<description>Peripheral DMA1 CH3 interrupt mask to CPU2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1_CH4_IM</name>
<description>Peripheral DMA1 CH4 interrupt mask to CPU2</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1_CH5_IM</name>
<description>Peripheral DMA1 CH5 interrupt mask to CPU2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1_CH6_IM</name>
<description>Peripheral DMA1 CH6 interrupt mask to CPU2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA1_CH7_IM</name>
<description>Peripheral DMA1 CH7 interrupt mask to CPU2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH1_IM</name>
<description>Peripheral DMA2 CH1 interrupt mask to CPU1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH2_IM</name>
<description>Peripheral DMA2 CH2 interrupt mask to CPU1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH3_IM</name>
<description>Peripheral DMA2 CH3 interrupt mask to CPU1</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH4_IM</name>
<description>Peripheral DMA2 CH4 interrupt mask to CPU1</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH5_IM</name>
<description>Peripheral DMA2 CH5 interrupt mask to CPU1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH6_IM</name>
<description>Peripheral DMA2 CH6 interrupt mask to CPU1</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA2_CH7_IM</name>
<description>Peripheral DMA2 CH7 interrupt mask to CPU1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAM_UX1_IM</name>
<description>Peripheral DMAM UX1 interrupt mask to CPU1</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVM1IM</name>
<description>Peripheral PVM1IM interrupt mask to CPU1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVM3IM</name>
<description>Peripheral PVM3IM interrupt mask to CPU1</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVDIM</name>
<description>Peripheral PVDIM interrupt mask to CPU1</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSCIM</name>
<description>Peripheral TSCIM interrupt mask to CPU1</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCDIM</name>
<description>Peripheral LCDIM interrupt mask to CPU1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SYSCFG_SIPCR</name>
<displayName>SYSCFG_SIPCR</displayName>
<description>secure IP control register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAES1</name>
<description>Enable AES1 KEY[7:0] security.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAES2</name>
<description>Enable AES2 security.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPKA</name>
<description>Enable PKA security</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRNG</name>
<description>Enable True RNG security</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>COMP</name>
<description>Comparator instance 1</description>
<groupName>COMP</groupName>
<baseAddress>0x40010200</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x9</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>COMP</name>
<description>COMP2 & COMP1 interrupt through
AIEC[21:20]</description>
<value>22</value>
</interrupt>
<registers>
<register>
<name>COMP1_CSR</name>
<displayName>COMP1_CSR</displayName>
<description>Comparator control and status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP1_EN</name>
<description>Comparator enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_PWRMODE</name>
<description>Comparator power mode</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_INMSEL</name>
<description>Comparator input minus selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_INPSEL</name>
<description>Comparator input plus selection</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_POLARITY</name>
<description>Comparator output polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_HYST</name>
<description>Comparator hysteresis</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_BLANKING</name>
<description>Comparator blanking source</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_BRGEN</name>
<description>Comparator voltage scaler enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_SCALEN</name>
<description>Comparator scaler bridge enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_INMESEL</name>
<description>Comparator input minus extended selection</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP1_VALUE</name>
<description>Comparator output level</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>COMP1_LOCK</name>
<description>Comparator lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COMP2_CSR</name>
<displayName>COMP2_CSR</displayName>
<description>Comparator 2 control and status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP2_EN</name>
<description>Comparator 2 enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_PWRMODE</name>
<description>Power Mode of the comparator 2</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_INMSEL</name>
<description>Comparator 2 input minus selection bits</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_INPSEL</name>
<description>Comparator 1 input plus selection bit</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_WINMODE</name>
<description>Windows mode selection bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_POLARITY</name>
<description>Comparator 2 polarity selection bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_HYST</name>
<description>Comparator 2 hysteresis selection bits</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_BLANKING</name>
<description>Comparator 2 blanking source selection bits</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_BRGEN</name>
<description>Scaler bridge enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_SCALEN</name>
<description>Voltage scaler enable bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_INMESEL</name>
<description>comparator 2 input minus extended selection bits.</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>COMP2_VALUE</name>
<description>Comparator 2 output status bit</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>COMP2_LOCK</name>
<description>CSR register lock bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RNG</name>
<description>Random number generator</description>
<groupName>RNG</groupName>
<baseAddress>0x58001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>True_RNG</name>
<description>True random number generator
interrupt</description>
<value>53</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNGEN</name>
<description>Random number generator enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IE</name>
<description>Interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYP</name>
<description>Bypass mode enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEIS</name>
<description>Seed error interrupt status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CEIS</name>
<description>Clock error interrupt status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SECS</name>
<description>Seed error current status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CECS</name>
<description>Clock error current status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DRDY</name>
<description>Data ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNDATA</name>
<description>Random data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AES1</name>
<description>Advanced encryption standard hardware accelerator 1</description>
<groupName>AES1</groupName>
<baseAddress>0x50060000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AES1</name>
<description>AES1 global interrupt</description>
<value>51</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NPBLB</name>
<description>Number of padding bytes in last block of payload</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>KEYSIZE</name>
<description>Key size selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHMOD2</name>
<description>AES chaining mode Bit2</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCMPH</name>
<description>Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMAOUTEN</name>
<description>Enable DMA management of data output phase</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAINEN</name>
<description>Enable DMA management of data input phase</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFIE</name>
<description>CCF flag interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFC</name>
<description>Computation Complete Flag Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHMOD10</name>
<description>AES chaining mode Bit1 Bit0</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>AES operating mode</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DATATYPE</name>
<description>Data type selection (for data in and data out to/from the cryptographic block)</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EN</name>
<description>AES enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BUSY</name>
<description>Busy flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRERR</name>
<description>Write error flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERR</name>
<description>Read error flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCF</name>
<description>Computation complete flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DINR</name>
<displayName>DINR</displayName>
<description>data input register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_DINR</name>
<description>Data Input Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOUTR</name>
<displayName>DOUTR</displayName>
<description>data output register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_DOUTR</name>
<description>Data output register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR0</name>
<displayName>KEYR0</displayName>
<description>key register 0</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR0</name>
<description>Data Output Register (LSB key [31:0])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR1</name>
<displayName>KEYR1</displayName>
<description>key register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR1</name>
<description>AES key register (key [63:32])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR2</name>
<displayName>KEYR2</displayName>
<description>key register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR2</name>
<description>AES key register (key [95:64])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR3</name>
<displayName>KEYR3</displayName>
<description>key register 3</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR3</name>
<description>AES key register (MSB key [127:96])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR0</name>
<displayName>IVR0</displayName>
<description>initialization vector register 0</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR0</name>
<description>initialization vector register (LSB IVR [31:0])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR1</name>
<displayName>IVR1</displayName>
<description>initialization vector register 1</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR1</name>
<description>Initialization Vector Register (IVR [63:32])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR2</name>
<displayName>IVR2</displayName>
<description>initialization vector register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR2</name>
<description>Initialization Vector Register (IVR [95:64])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR3</name>
<displayName>IVR3</displayName>
<description>initialization vector register 3</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR3</name>
<description>Initialization Vector Register (MSB IVR [127:96])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR4</name>
<displayName>KEYR4</displayName>
<description>key register 4</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR4</name>
<description>AES key register (MSB key [159:128])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR5</name>
<displayName>KEYR5</displayName>
<description>key register 5</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR5</name>
<description>AES key register (MSB key [191:160])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR6</name>
<displayName>KEYR6</displayName>
<description>key register 6</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR6</name>
<description>AES key register (MSB key [223:192])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR7</name>
<displayName>KEYR7</displayName>
<description>key register 7</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR7</name>
<description>AES key register (MSB key [255:224])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP0R</name>
<displayName>SUSP0R</displayName>
<description>AES suspend register 0</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP0R</name>
<description>AES suspend register 0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP1R</name>
<displayName>SUSP1R</displayName>
<description>AES suspend register 1</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP1R</name>
<description>AES suspend register 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP2R</name>
<displayName>SUSP2R</displayName>
<description>AES suspend register 2</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP2R</name>
<description>AES suspend register 2</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP3R</name>
<displayName>SUSP3R</displayName>
<description>AES suspend register 3</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP3R</name>
<description>AES suspend register 3</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP4R</name>
<displayName>SUSP4R</displayName>
<description>AES suspend register 4</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP4R</name>
<description>AES suspend register 4</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP5R</name>
<displayName>SUSP5R</displayName>
<description>AES suspend register 5</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP5R</name>
<description>AES suspend register 5</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP6R</name>
<displayName>SUSP6R</displayName>
<description>AES suspend register 6</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP6R</name>
<description>AES suspend register 6</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP7R</name>
<displayName>SUSP7R</displayName>
<description>AES suspend register 7</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP7R</name>
<description>AES suspend register 7</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFR</name>
<displayName>HWCFR</displayName>
<description>AES hardware configuration register</description>
<addressOffset>0x3F0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>CFG4</name>
<description>HW Generic 4</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CFG3</name>
<description>HW Generic 3</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CFG2</name>
<description>HW Generic 2</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CFG1</name>
<description>HW Generic 1</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>AES version register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>MAJREV</name>
<description>Major revision</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MINREV</name>
<description>Minor revision</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPIDR</name>
<displayName>IPIDR</displayName>
<description>AES identification register</description>
<addressOffset>0x3F8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00170023</resetValue>
<fields>
<field>
<name>ID</name>
<description>Identification code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>AES size ID register</description>
<addressOffset>0x3FC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD01</resetValue>
<fields>
<field>
<name>ID</name>
<description>Size Identification code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>AES2</name>
<description>Advanced encryption standard hardware accelerator 1</description>
<groupName>AES1</groupName>
<baseAddress>0x58001800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>AES2</name>
<description>AES2 global interrupt</description>
<value>52</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NPBLB</name>
<description>Number of padding bytes in last block of payload</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>KEYSIZE</name>
<description>Key size selection</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHMOD2</name>
<description>AES chaining mode Bit2</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GCMPH</name>
<description>Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMAOUTEN</name>
<description>Enable DMA management of data output phase</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAINEN</name>
<description>Enable DMA management of data input phase</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFIE</name>
<description>CCF flag interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCFC</name>
<description>Computation Complete Flag Clear</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHMOD10</name>
<description>AES chaining mode Bit1 Bit0</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>AES operating mode</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DATATYPE</name>
<description>Data type selection (for data in and data out to/from the cryptographic block)</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EN</name>
<description>AES enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BUSY</name>
<description>Busy flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRERR</name>
<description>Write error flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDERR</name>
<description>Read error flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCF</name>
<description>Computation complete flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DINR</name>
<displayName>DINR</displayName>
<description>data input register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_DINR</name>
<description>Data Input Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOUTR</name>
<displayName>DOUTR</displayName>
<description>data output register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_DOUTR</name>
<description>Data output register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR0</name>
<displayName>KEYR0</displayName>
<description>key register 0</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR0</name>
<description>Data Output Register (LSB key [31:0])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR1</name>
<displayName>KEYR1</displayName>
<description>key register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR1</name>
<description>AES key register (key [63:32])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR2</name>
<displayName>KEYR2</displayName>
<description>key register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR2</name>
<description>AES key register (key [95:64])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR3</name>
<displayName>KEYR3</displayName>
<description>key register 3</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR3</name>
<description>AES key register (MSB key [127:96])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR0</name>
<displayName>IVR0</displayName>
<description>initialization vector register 0</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR0</name>
<description>initialization vector register (LSB IVR [31:0])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR1</name>
<displayName>IVR1</displayName>
<description>initialization vector register 1</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR1</name>
<description>Initialization Vector Register (IVR [63:32])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR2</name>
<displayName>IVR2</displayName>
<description>initialization vector register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR2</name>
<description>Initialization Vector Register (IVR [95:64])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IVR3</name>
<displayName>IVR3</displayName>
<description>initialization vector register 3</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_IVR3</name>
<description>Initialization Vector Register (MSB IVR [127:96])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR4</name>
<displayName>KEYR4</displayName>
<description>key register 4</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR4</name>
<description>AES key register (MSB key [159:128])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR5</name>
<displayName>KEYR5</displayName>
<description>key register 5</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR5</name>
<description>AES key register (MSB key [191:160])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR6</name>
<displayName>KEYR6</displayName>
<description>key register 6</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR6</name>
<description>AES key register (MSB key [223:192])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR7</name>
<displayName>KEYR7</displayName>
<description>key register 7</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_KEYR7</name>
<description>AES key register (MSB key [255:224])</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP0R</name>
<displayName>SUSP0R</displayName>
<description>AES suspend register 0</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP0R</name>
<description>AES suspend register 0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP1R</name>
<displayName>SUSP1R</displayName>
<description>AES suspend register 1</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP1R</name>
<description>AES suspend register 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP2R</name>
<displayName>SUSP2R</displayName>
<description>AES suspend register 2</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP2R</name>
<description>AES suspend register 2</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP3R</name>
<displayName>SUSP3R</displayName>
<description>AES suspend register 3</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP3R</name>
<description>AES suspend register 3</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP4R</name>
<displayName>SUSP4R</displayName>
<description>AES suspend register 4</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP4R</name>
<description>AES suspend register 4</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP5R</name>
<displayName>SUSP5R</displayName>
<description>AES suspend register 5</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP5R</name>
<description>AES suspend register 5</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP6R</name>
<displayName>SUSP6R</displayName>
<description>AES suspend register 6</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP6R</name>
<description>AES suspend register 6</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SUSP7R</name>
<displayName>SUSP7R</displayName>
<description>AES suspend register 7</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AES_SUSP7R</name>
<description>AES suspend register 7</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFR</name>
<displayName>HWCFR</displayName>
<description>AES hardware configuration register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>CFG4</name>
<description>HW Generic 4</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CFG3</name>
<description>HW Generic 3</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CFG2</name>
<description>HW Generic 2</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CFG1</name>
<description>HW Generic 1</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>AES version register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>MAJREV</name>
<description>Major revision</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MINREV</name>
<description>Minor revision</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPIDR</name>
<displayName>IPIDR</displayName>
<description>AES identification register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00170023</resetValue>
<fields>
<field>
<name>ID</name>
<description>Identification code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>AES size ID register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00170023</resetValue>
<fields>
<field>
<name>ID</name>
<description>Size Identification code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HSEM</name>
<description>HSEM</description>
<groupName>Hardware_Semaphore</groupName>
<baseAddress>0x58001400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>HSEM</name>
<description>Semaphore interrupt 0 to CPU1</description>
<value>46</value>
</interrupt>
<registers>
<register>
<name>R0</name>
<displayName>R0</displayName>
<description>Semaphore 0 register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R1</name>
<displayName>R1</displayName>
<description>Semaphore 1 register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R2</name>
<displayName>R2</displayName>
<description>Semaphore 2 register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R3</name>
<displayName>R3</displayName>
<description>Semaphore 3 register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R4</name>
<displayName>R4</displayName>
<description>Semaphore 4 register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R5</name>
<displayName>R5</displayName>
<description>Semaphore 5 register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R6</name>
<displayName>R6</displayName>
<description>Semaphore 6 register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R7</name>
<displayName>R7</displayName>
<description>Semaphore 7 register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R8</name>
<displayName>R8</displayName>
<description>Semaphore 8 register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R9</name>
<displayName>R9</displayName>
<description>Semaphore 9 register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R10</name>
<displayName>R10</displayName>
<description>Semaphore 10 register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R11</name>
<displayName>R11</displayName>
<description>Semaphore 11 register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R12</name>
<displayName>R12</displayName>
<description>Semaphore 12 register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R13</name>
<displayName>R13</displayName>
<description>Semaphore 13 register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R14</name>
<displayName>R14</displayName>
<description>Semaphore 14 register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R15</name>
<displayName>R15</displayName>
<description>Semaphore 15 register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R16</name>
<displayName>R16</displayName>
<description>Semaphore 16 register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R17</name>
<displayName>R17</displayName>
<description>Semaphore 17 register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R18</name>
<displayName>R18</displayName>
<description>Semaphore 18 register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R19</name>
<displayName>R19</displayName>
<description>Semaphore 19 register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R20</name>
<displayName>R20</displayName>
<description>Semaphore 20 register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R21</name>
<displayName>R21</displayName>
<description>Semaphore 21 register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R22</name>
<displayName>R22</displayName>
<description>Semaphore 22 register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R23</name>
<displayName>R23</displayName>
<description>Semaphore 23 register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R24</name>
<displayName>R24</displayName>
<description>Semaphore 24 register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R25</name>
<displayName>R25</displayName>
<description>Semaphore 25 register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R26</name>
<displayName>R26</displayName>
<description>Semaphore 26 register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R27</name>
<displayName>R27</displayName>
<description>Semaphore 27 register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R28</name>
<displayName>R28</displayName>
<description>Semaphore 28 register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R29</name>
<displayName>R29</displayName>
<description>Semaphore 29 register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R30</name>
<displayName>R30</displayName>
<description>Semaphore 30 register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>R31</name>
<displayName>R31</displayName>
<description>Semaphore 31 register</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR0</name>
<displayName>RLR0</displayName>
<description>Semaphore 0 read lock register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR1</name>
<displayName>RLR1</displayName>
<description>Semaphore 1 read lock register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR2</name>
<displayName>RLR2</displayName>
<description>Semaphore 2 read lock register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR3</name>
<displayName>RLR3</displayName>
<description>Semaphore 3 read lock register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR4</name>
<displayName>RLR4</displayName>
<description>Semaphore 4 read lock read lock register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR5</name>
<displayName>RLR5</displayName>
<description>Semaphore 5 read lock register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR6</name>
<displayName>RLR6</displayName>
<description>Semaphore 6 read lock register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR7</name>
<displayName>RLR7</displayName>
<description>Semaphore 7 read lock register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR8</name>
<displayName>RLR8</displayName>
<description>Semaphore 8 read lock register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR9</name>
<displayName>RLR9</displayName>
<description>Semaphore 9 read lock register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR10</name>
<displayName>RLR10</displayName>
<description>Semaphore 10 read lock register</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR11</name>
<displayName>RLR11</displayName>
<description>Semaphore 11 read lock register</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR12</name>
<displayName>RLR12</displayName>
<description>Semaphore 12 read lock register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR13</name>
<displayName>RLR13</displayName>
<description>Semaphore 13 read lock register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR14</name>
<displayName>RLR14</displayName>
<description>Semaphore 14 read lock register</description>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR15</name>
<displayName>RLR15</displayName>
<description>Semaphore 15 read lock register</description>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR16</name>
<displayName>RLR16</displayName>
<description>Semaphore 16 read lock register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR17</name>
<displayName>RLR17</displayName>
<description>Semaphore 17 read lock register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR18</name>
<displayName>RLR18</displayName>
<description>Semaphore 18 read lock register</description>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR19</name>
<displayName>RLR19</displayName>
<description>Semaphore 19 read lock register</description>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR20</name>
<displayName>RLR20</displayName>
<description>Semaphore 20 read lock register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR21</name>
<displayName>RLR21</displayName>
<description>Semaphore 21 read lock register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR22</name>
<displayName>RLR22</displayName>
<description>Semaphore 22 read lock register</description>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR23</name>
<displayName>RLR23</displayName>
<description>Semaphore 23 read lock register</description>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR24</name>
<displayName>RLR24</displayName>
<description>Semaphore 24 read lock register</description>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR25</name>
<displayName>RLR25</displayName>
<description>Semaphore 25 read lock register</description>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR26</name>
<displayName>RLR26</displayName>
<description>Semaphore 26 read lock register</description>
<addressOffset>0xE8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR27</name>
<displayName>RLR27</displayName>
<description>Semaphore 27 read lock register</description>
<addressOffset>0xEC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR28</name>
<displayName>RLR28</displayName>
<description>Semaphore 28 read lock register</description>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR29</name>
<displayName>RLR29</displayName>
<description>Semaphore 29 read lock register</description>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR30</name>
<displayName>RLR30</displayName>
<description>Semaphore 30 read lock register</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RLR31</name>
<displayName>RLR31</displayName>
<description>Semaphore 31 read lock register</description>
<addressOffset>0xFC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOCK</name>
<description>lock indication</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COREID</name>
<description>Semaphore CoreID</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PROCID</name>
<description>Semaphore ProcessID</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Semaphore Clear register</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Semaphore clear Key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>COREID</name>
<description>CoreID of semaphore to be cleared</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>KEYR</name>
<displayName>KEYR</displayName>
<description>Interrupt clear register</description>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Semaphore Clear Key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR2</name>
<displayName>HWCFGR2</displayName>
<description>Semaphore hardware configuration register 2</description>
<addressOffset>0x3EC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000084</resetValue>
<fields>
<field>
<name>MASTERID4</name>
<description>Hardware Configuration valid bus masters ID4</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MASTERID3</name>
<description>Hardware Configuration valid bus masters ID3</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MASTERID2</name>
<description>Hardware Configuration valid bus masters ID2</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MASTERID1</name>
<description>Hardware Configuration valid bus masters ID1</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR1</name>
<displayName>HWCFGR1</displayName>
<description>Semaphore hardware configuration register 1</description>
<addressOffset>0x3F0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000220</resetValue>
<fields>
<field>
<name>NBINT</name>
<description>Hardware Configuration number of interrupts supported number of master IDs</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>NBSEM</name>
<description>Hardware Configuration number of semaphores</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>HSEM version register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000020</resetValue>
<fields>
<field>
<name>MAJREV</name>
<description>Major Revision</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MINREV</name>
<description>Minor Revision</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPIDR</name>
<displayName>IPIDR</displayName>
<description>HSEM indentification register</description>
<addressOffset>0x3F8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00100072</resetValue>
<fields>
<field>
<name>ID</name>
<description>Identification Code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>HSEM size indentification register</description>
<addressOffset>0x3FC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD01</resetValue>
<fields>
<field>
<name>SID</name>
<description>Size Identification Code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1IER0</name>
<displayName>C1IER0</displayName>
<description>HSEM Interrupt enable register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISEm</name>
<description>CPU(n) semaphore m enable bit</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1ICR</name>
<displayName>C1ICR</displayName>
<description>HSEM Interrupt clear register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISCm</name>
<description>CPU(n) semaphore m clear bit</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1ISR</name>
<displayName>C1ISR</displayName>
<description>HSEM Interrupt status register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISFm</name>
<description>CPU(n) semaphore m status bit before enable (mask)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1MISR</name>
<displayName>C1MISR</displayName>
<description>HSEM Masked interrupt status register</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MISFm</name>
<description>masked CPU(n) semaphore m status bit after enable (mask).</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2IER0</name>
<displayName>C2IER0</displayName>
<description>HSEM Interrupt enable register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISEm</name>
<description>CPU(2) semaphore m enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2ICR</name>
<displayName>C2ICR</displayName>
<description>HSEM Interrupt clear register</description>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISCm</name>
<description>CPU(2) semaphore m clear bit</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2ISR</name>
<displayName>C2ISR</displayName>
<description>HSEM Interrupt status register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ISFm</name>
<description>CPU(2) semaphore m status bit before enable (mask).</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2MISR</name>
<displayName>C2MISR</displayName>
<description>HSEM Masked interrupt status register</description>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MISFm</name>
<description>masked CPU(2) semaphore m status bit after enable (mask).</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC</name>
<description>Analog to Digital Converter instance 1</description>
<groupName>ADC</groupName>
<baseAddress>0x50040000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC1</name>
<description>ADC1 global interrupt</description>
<value>18</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>ADC interrupt and status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVF</name>
<description>ADC group injected contexts queue overflow flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3</name>
<description>ADC analog watchdog 3 flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2</name>
<description>ADC analog watchdog 2 flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1</name>
<description>ADC analog watchdog 1 flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOS</name>
<description>ADC group injected end of sequence conversions flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC</name>
<description>ADC group injected end of unitary conversion flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR</name>
<description>ADC group regular overrun flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOS</name>
<description>ADC group regular end of sequence conversions flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC</name>
<description>ADC group regular end of unitary conversion flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMP</name>
<description>ADC group regular end of sampling flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDY</name>
<description>ADC ready flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>ADC interrupt enable register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JQOVFIE</name>
<description>ADC group injected contexts queue overflow interrupt</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3IE</name>
<description>ADC analog watchdog 3 interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2IE</name>
<description>ADC analog watchdog 2 interrupt</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1IE</name>
<description>ADC analog watchdog 1 interrupt</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOSIE</name>
<description>ADC group injected end of sequence conversions interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOCIE</name>
<description>ADC group injected end of unitary conversion interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRIE</name>
<description>ADC group regular overrun interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSIE</name>
<description>ADC group regular end of sequence conversions interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCIE</name>
<description>ADC group regular end of unitary conversion interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOSMPIE</name>
<description>ADC group regular end of sampling interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADRDYIE</name>
<description>ADC ready interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>ADC control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADCAL</name>
<description>ADC calibration</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCALDIF</name>
<description>ADC differential mode for calibration</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEEPPWD</name>
<description>ADC deep power down enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADVREGEN</name>
<description>ADC voltage regulator enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTP</name>
<description>ADC group injected conversion stop</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTP</name>
<description>ADC group regular conversion stop</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JADSTART</name>
<description>ADC group injected conversion start</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADSTART</name>
<description>ADC group regular conversion start</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDIS</name>
<description>ADC disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADEN</name>
<description>ADC enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>ADC configuration register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<fields>
<field>
<name>JQDIS</name>
<description>ADC group injected contexts queue disable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWDCH1CH</name>
<description>ADC analog watchdog 1 monitored channel selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JAUTO</name>
<description>ADC group injected automatic trigger mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JAWD1EN</name>
<description>ADC analog watchdog 1 enable on scope ADC group injected</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1EN</name>
<description>ADC analog watchdog 1 enable on scope ADC group regular</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1SGL</name>
<description>ADC analog watchdog 1 monitoring a single channel or all channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JQM</name>
<description>ADC group injected contexts queue mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JDISCEN</name>
<description>ADC group injected sequencer discontinuous mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCNUM</name>
<description>ADC group regular sequencer discontinuous number of ranks</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DISCEN</name>
<description>ADC group regular sequencer discontinuous mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTDLY</name>
<description>ADC low power auto wait</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>ADC group regular continuous conversion mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRMOD</name>
<description>ADC group regular overrun configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEN</name>
<description>ADC group regular external trigger polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EXTSEL</name>
<description>ADC group regular external trigger source</description>
<bitOffset>6</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ALIGN</name>
<description>ADC data alignement</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RES</name>
<description>ADC data resolution</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMACFG</name>
<description>ADC DMA transfer configuration</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>ADC DMA transfer enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR2</name>
<displayName>CFGR2</displayName>
<description>ADC configuration register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROVSM</name>
<description>ADC oversampling mode managing interlaced conversions of ADC group regular and group injected</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOVS</name>
<description>ADC oversampling discontinuous mode (triggered mode) for ADC group regular</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVSS</name>
<description>ADC oversampling shift</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OVSR</name>
<description>ADC oversampling ratio</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>JOVSE</name>
<description>ADC oversampler enable on scope ADC group injected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROVSE</name>
<description>ADC oversampler enable on scope ADC group regular</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR1</name>
<displayName>SMPR1</displayName>
<description>ADC sampling time register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP9</name>
<description>ADC channel 9 sampling time selection</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP8</name>
<description>ADC channel 8 sampling time selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP7</name>
<description>ADC channel 7 sampling time selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP6</name>
<description>ADC channel 6 sampling time selection</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP5</name>
<description>ADC channel 5 sampling time selection</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP4</name>
<description>ADC channel 4 sampling time selection</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP3</name>
<description>ADC channel 3 sampling time selection</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP2</name>
<description>ADC channel 2 sampling time selection</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP1</name>
<description>ADC channel 1 sampling time selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR2</name>
<displayName>SMPR2</displayName>
<description>ADC sampling time register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP18</name>
<description>ADC channel 18 sampling time selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP17</name>
<description>ADC channel 17 sampling time selection</description>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP16</name>
<description>ADC channel 16 sampling time selection</description>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP15</name>
<description>ADC channel 15 sampling time selection</description>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP14</name>
<description>ADC channel 14 sampling time selection</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP13</name>
<description>ADC channel 13 sampling time selection</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP12</name>
<description>ADC channel 12 sampling time selection</description>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP11</name>
<description>ADC channel 11 sampling time selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMP10</name>
<description>ADC channel 10 sampling time selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TR1</name>
<displayName>TR1</displayName>
<description>ADC analog watchdog 1 threshold register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>HT1</name>
<description>ADC analog watchdog 1 threshold high</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>LT1</name>
<description>ADC analog watchdog 1 threshold low</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>TR2</name>
<displayName>TR2</displayName>
<description>ADC analog watchdog 2 threshold register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>HT2</name>
<description>ADC analog watchdog 2 threshold high</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LT2</name>
<description>ADC analog watchdog 2 threshold low</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TR3</name>
<displayName>TR3</displayName>
<description>ADC analog watchdog 3 threshold register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>HT3</name>
<description>ADC analog watchdog 3 threshold high</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LT3</name>
<description>ADC analog watchdog 3 threshold low</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR1</name>
<displayName>SQR1</displayName>
<description>ADC group regular sequencer ranks register 1</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ4</name>
<description>ADC group regular sequencer rank 4</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ3</name>
<description>ADC group regular sequencer rank 3</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ2</name>
<description>ADC group regular sequencer rank 2</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ1</name>
<description>ADC group regular sequencer rank 1</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>L3</name>
<description>L3</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR2</name>
<displayName>SQR2</displayName>
<description>ADC group regular sequencer ranks register 2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ9</name>
<description>ADC group regular sequencer rank 9</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ8</name>
<description>ADC group regular sequencer rank 8</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ7</name>
<description>ADC group regular sequencer rank 7</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ6</name>
<description>ADC group regular sequencer rank 6</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ5</name>
<description>ADC group regular sequencer rank 5</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR3</name>
<displayName>SQR3</displayName>
<description>ADC group regular sequencer ranks register 3</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ14</name>
<description>ADC group regular sequencer rank 14</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ13</name>
<description>ADC group regular sequencer rank 13</description>
<bitOffset>18</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ12</name>
<description>ADC group regular sequencer rank 12</description>
<bitOffset>12</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ11</name>
<description>ADC group regular sequencer rank 11</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ10</name>
<description>ADC group regular sequencer rank 10</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR4</name>
<displayName>SQR4</displayName>
<description>ADC group regular sequencer ranks register 4</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ16</name>
<description>ADC group regular sequencer rank 16</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ15</name>
<description>ADC group regular sequencer rank 15</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>ADC group regular conversion data register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RDATA_0_6</name>
<description>Regular Data converted 0_6</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RDATA_7_15</name>
<description>15</description>
<bitOffset>7</bitOffset>
<bitWidth>9</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>JSQR</name>
<displayName>JSQR</displayName>
<description>ADC group injected sequencer register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JSQ4</name>
<description>ADC group injected sequencer rank 4</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ3</name>
<description>ADC group injected sequencer rank 3</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ2</name>
<description>ADC group injected sequencer rank 2</description>
<bitOffset>14</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ1</name>
<description>ADC group injected sequencer rank 1</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JEXTEN</name>
<description>ADC group injected external trigger polarity</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>JEXTSEL</name>
<description>ADC group injected external trigger source</description>
<bitOffset>2</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>JL</name>
<description>ADC group injected sequencer scan length</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR1</name>
<displayName>OFR1</displayName>
<description>ADC offset number 1 register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET1_EN</name>
<description>ADC offset number 1 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET1_CH</name>
<description>ADC offset number 1 channel selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET1</name>
<description>ADC offset number 1 offset level</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR2</name>
<displayName>OFR2</displayName>
<description>ADC offset number 2 register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET2_EN</name>
<description>ADC offset number 2 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET2_CH</name>
<description>ADC offset number 2 channel selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET2</name>
<description>ADC offset number 2 offset level</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR3</name>
<displayName>OFR3</displayName>
<description>ADC offset number 3 register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET3_EN</name>
<description>ADC offset number 3 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET3_CH</name>
<description>ADC offset number 3 channel selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET3</name>
<description>ADC offset number 3 offset level</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OFR4</name>
<displayName>OFR4</displayName>
<description>ADC offset number 4 register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OFFSET4_EN</name>
<description>ADC offset number 4 enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFSET4_CH</name>
<description>ADC offset number 4 channel selection</description>
<bitOffset>26</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>OFFSET4</name>
<description>ADC offset number 4 offset level</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR1</name>
<displayName>JDR1</displayName>
<description>ADC group injected sequencer rank 1 register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA1</name>
<description>ADC group injected sequencer rank 1 conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR2</name>
<displayName>JDR2</displayName>
<description>ADC group injected sequencer rank 2 register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA2</name>
<description>ADC group injected sequencer rank 2 conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR3</name>
<displayName>JDR3</displayName>
<description>ADC group injected sequencer rank 3 register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA3</name>
<description>ADC group injected sequencer rank 3 conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR4</name>
<displayName>JDR4</displayName>
<description>ADC group injected sequencer rank 4 register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA4</name>
<description>ADC group injected sequencer rank 4 conversion data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD2CR</name>
<displayName>AWD2CR</displayName>
<description>ADC analog watchdog 2 configuration register</description>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD2CH</name>
<description>ADC analog watchdog 2 monitored channel selection</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>AWD3CR</name>
<displayName>AWD3CR</displayName>
<description>ADC analog watchdog 3 configuration register</description>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AWD3CH</name>
<description>ADC analog watchdog 3 monitored channel selection</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIFSEL</name>
<displayName>DIFSEL</displayName>
<description>ADC channel differential or single-ended mode selection register</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIFSEL_0</name>
<description>ADC channel differential or single-ended mode for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIFSEL_1_15</name>
<description>ADC channel differential or single-ended mode for channels 1 to 15</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIFSEL_16_18</name>
<description>ADC channel differential or single-ended mode for channels 18 to 16</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CALFACT</name>
<displayName>CALFACT</displayName>
<description>ADC calibration factors register</description>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALFACT_D</name>
<description>ADC calibration factor in differential mode</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>CALFACT_S</name>
<description>ADC calibration factor in single-ended mode</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>ADC common control register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VBATEN</name>
<description>VBAT enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSEN</name>
<description>Temperature sensor enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VREFEN</name>
<description>VREFEN</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>ADC prescaler</description>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CKMODE</name>
<description>ADC clock mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xABFFFFFF</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0C000000</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x64000000</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL7</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL6</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL5</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port Reset bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port Reset bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port Reset bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port Reset bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port Reset bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port Reset bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port Reset bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port Reset bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port Reset bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port Reset bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port Reset bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOB</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFEBF</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000C0</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000100</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL7</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL6</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL5</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port Reset bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port Reset bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port Reset bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port Reset bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port Reset bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port Reset bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port Reset bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port Reset bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port Reset bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port Reset bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port Reset bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOC</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48000800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000C0</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000100</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL7</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL6</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL5</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR5</name>
<description>Port Reset bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR6</name>
<description>Port Reset bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR7</name>
<description>Port Reset bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR8</name>
<description>Port Reset bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR9</name>
<description>Port Reset bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR10</name>
<description>Port Reset bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR11</name>
<description>Port Reset bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR12</name>
<description>Port Reset bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR13</name>
<description>Port Reset bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR14</name>
<description>Port Reset bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR15</name>
<description>Port Reset bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIOC">
<name>GPIOD</name>
<baseAddress>0x48000C00</baseAddress>
</peripheral>
<peripheral>
<name>GPIOE</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000003FF</resetValue>
<fields>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000C0</resetValue>
<fields>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR4</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR4</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR4</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL4</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL2</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR2</name>
<description>Port Reset bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR4</name>
<description>Port Reset bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOH</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x48001C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000CF</resetValue>
<fields>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR3</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR3</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y = 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR3</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y = 0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y= 0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL3</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL1</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL0</name>
<description>Alternate function selection for port x bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFSEL15</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL14</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL13</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL12</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL11</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL10</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL9</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AFSEL8</name>
<description>Alternate function selection for port x bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>port bit reset register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR0</name>
<description>Port Reset bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR1</name>
<description>Port Reset bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR3</name>
<description>Port Reset bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SAI1</name>
<description>Serial audio interface</description>
<groupName>SAI</groupName>
<baseAddress>0x40015400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SAI1</name>
<description>SAI1 global interrupt</description>
<value>38</value>
</interrupt>
<registers>
<register>
<name>GCR</name>
<displayName>GCR</displayName>
<description>Global configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOUT</name>
<description>Synchronization outputs</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCIN</name>
<description>Synchronization inputs</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCR1</name>
<displayName>BCR1</displayName>
<description>BConfiguration register 1</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MCKEN</name>
<description>Master clock generation enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSR</name>
<description>Oversampling ratio for master clock</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCJDIV</name>
<description>Master clock divider</description>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NODIV</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAIBEN</name>
<description>Audio block B enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OutDri</name>
<description>Output drive</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONO</name>
<description>Mono mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit first</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>Audio block mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCR2</name>
<displayName>BCR2</displayName>
<description>BConfiguration register 2</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP</name>
<description>Companding mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CPL</name>
<description>Complement bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTECN</name>
<description>Mute counter</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTE</name>
<description>Mute</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFLUS</name>
<description>FIFO flush</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFRCR</name>
<displayName>BFRCR</displayName>
<description>BFRCR</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FSOFF</name>
<description>Frame synchronization offset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization definition</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level length</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FRL</name>
<description>Frame length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSLOTR</name>
<displayName>BSLOTR</displayName>
<description>BSlot register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLOTEN</name>
<description>Slot enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FBOFF</name>
<description>First bit offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>BIM</name>
<displayName>BIM</displayName>
<description>BInterrupt mask register2</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDETIE</name>
<description>Late frame synchronization detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization detection interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BSR</name>
<displayName>BSR</displayName>
<description>BStatus register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000008</resetValue>
<fields>
<field>
<name>FLVL</name>
<description>FIFO level threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization detection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQ</name>
<description>FIFO request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BCLRFR</name>
<displayName>BCLRFR</displayName>
<description>BClear flag register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDET</name>
<description>Clear late frame synchronization detection flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization detection flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Clear codec not ready flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Clear wrong clock configuration flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Clear overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDR</name>
<displayName>BDR</displayName>
<description>BData register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR1</name>
<displayName>ACR1</displayName>
<description>AConfiguration register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MCKEN</name>
<description>Master clock generation enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSR</name>
<description>Oversampling ratio for master clock</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCJDIV</name>
<description>Master clock divider</description>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NODIV</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAIBEN</name>
<description>Audio block B enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OutDri</name>
<description>Output drive</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONO</name>
<description>Mono mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit first</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MODE</name>
<description>Audio block mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACR2</name>
<displayName>ACR2</displayName>
<description>AConfiguration register 2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP</name>
<description>Companding mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CPL</name>
<description>Complement bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTECN</name>
<description>Mute counter</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTE</name>
<description>Mute</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFLUS</name>
<description>FIFO flush</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFRCR</name>
<displayName>AFRCR</displayName>
<description>AFRCR</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FSOFF</name>
<description>Frame synchronization offset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization definition</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level length</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FRL</name>
<description>Frame length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ASLOTR</name>
<displayName>ASLOTR</displayName>
<description>ASlot register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLOTEN</name>
<description>Slot enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FBOFF</name>
<description>First bit offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIM</name>
<displayName>AIM</displayName>
<description>AInterrupt mask register2</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization detection interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ASR</name>
<displayName>ASR</displayName>
<description>AStatus register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000008</resetValue>
<fields>
<field>
<name>FLVL</name>
<description>FIFO level threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization detection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization detection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREQ</name>
<description>FIFO request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag. This bit is read only</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACLRFR</name>
<displayName>ACLRFR</displayName>
<description>AClear flag register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDET</name>
<description>Clear late frame synchronization detection flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization detection flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNRDY</name>
<description>Clear codec not ready flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WCKCFG</name>
<description>Clear wrong clock configuration flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRUDR</name>
<description>Clear overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADR</name>
<displayName>ADR</displayName>
<description>AData register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDMCR</name>
<displayName>PDMCR</displayName>
<description>PDM control register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CKEN4</name>
<description>Clock enable of bitstream clock number 4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN3</name>
<description>Clock enable of bitstream clock number 3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN2</name>
<description>Clock enable of bitstream clock number 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKEN1</name>
<description>Clock enable of bitstream clock number 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MICNBR</name>
<description>Number of microphones</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PDMEN</name>
<description>PDM enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDMDLY</name>
<displayName>PDMDLY</displayName>
<description>PDM delay register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DLYM4R</name>
<description>Delay line for second microphone of pair 4</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM4L</name>
<description>Delay line for first microphone of pair 4</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM3R</name>
<description>Delay line for second microphone of pair 3</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM3L</name>
<description>Delay line for first microphone of pair 3</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM2R</name>
<description>Delay line for second microphone of pair 2</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM2L</name>
<description>Delay line for first microphone of pair 2</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM1R</name>
<description>Delay line for second microphone of pair 1</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DLYM1L</name>
<description>Delay line for first microphone of pair 1</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM2</name>
<description>General-purpose-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM2</name>
<description>TIM2 global interrupt</description>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OCCS</name>
<description>OCREF clear selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4 generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3 generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2 generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>Output compare 2 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output compare 2 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output compare 2 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>Output compare 1 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4M_3</name>
<description>Output Compare 4 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 3 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/Compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/Compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 output Polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_H</name>
<description>High counter value (TIM2 only)</description>
<bitOffset>16</bitOffset>
<bitWidth>15</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNT_L</name>
<description>Low counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>Value depends on IUFREMAP in TIM2_CR1.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR_H</name>
<description>High Auto-reload value (TIM2 only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ARR_L</name>
<description>Low Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1_H</name>
<description>High Capture/Compare 1 value (TIM2 only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR1_L</name>
<description>Low Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2_H</name>
<description>High Capture/Compare 2 value (TIM2 only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR2_L</name>
<description>Low Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3_H</name>
<description>High Capture/Compare value (TIM2 only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR3_L</name>
<description>Low Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4_H</name>
<description>High Capture/Compare value (TIM2 only)</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR4_L</name>
<description>Low Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>TIM2 option register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI4_RMP</name>
<description>Input capture 4 remap</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ETR_RMP</name>
<description>External trigger remap</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITR_RMP</name>
<description>Internal trigger remap</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF</name>
<displayName>AF</displayName>
<description>TIM2 alternate function option register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ETRSEL</name>
<description>External trigger source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM16</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDSRM</name>
<description>Break Disarm</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKBID</name>
<description>Break Bidirectional</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR1</name>
<displayName>OR1</displayName>
<description>TIM option register 1</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1_RMP</name>
<description>Input capture 1 remap</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>alternate function register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>input selection register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15] input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM17</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF Copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKDSRM</name>
<description>Break Disarm</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKBID</name>
<description>Break Bidirectional</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR1</name>
<displayName>OR1</displayName>
<description>TIM option register 1</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1_RMP</name>
<description>Input capture 1 remap</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>alternate function register 1</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TISEL</name>
<displayName>TISEL</displayName>
<description>input selection register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TI1SEL</name>
<description>selects TI1[0] to TI1[15] input</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM1</name>
<description>Advanced-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40012C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM1_BRK</name>
<description>Timer 1 break interrupt</description>
<value>24</value>
</interrupt>
<interrupt>
<name>TIM1_UP</name>
<description>Timer 1 Update</description>
<value>25</value>
</interrupt>
<interrupt>
<name>TIM1_TRG_COM_TIM17</name>
<description>TIM1 Trigger and Commutation interrupts and
TIM17 global interrupt</description>
<value>26</value>
</interrupt>
<interrupt>
<name>TIM1_CC</name>
<description>TIM1 Capture Compare interrupt</description>
<value>27</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>UIFREMAP</name>
<description>UIF status bit remapping</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MMS2</name>
<description>Master mode selection 2</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>OIS6</name>
<description>Output Idle state 6 (OC6 output)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS5</name>
<description>Output Idle state 5 (OC5 output)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS4</name>
<description>Output Idle state 4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3N</name>
<description>Output Idle state 3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3</name>
<description>Output Idle state 3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2N</name>
<description>Output Idle state 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OCCS</name>
<description>OCREF clear selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMS_3</name>
<description>Slave mode selection - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2IF</name>
<description>Break 2 interrupt flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBIF</name>
<description>System Break interrupt flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5IF</name>
<description>Compare 5 interrupt flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6IF</name>
<description>Compare 6 interrupt flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1 generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2 generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3 generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4 generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2G</name>
<description>Break 2 generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (output mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output mode)</description>
<alternateRegister>CCMR1_Input</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC1S</name>
<description>Capture/Compare 1 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC1CE</name>
<description>Output Compare 1 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC2CE</name>
<description>Output Compare 2 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M_3</name>
<description>Output Compare 1 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M_3</name>
<description>Output Compare 2 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC3S</name>
<description>Capture/Compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M_3</name>
<description>Output Compare 3 mode - bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M_3</name>
<description>Output Compare 4 mode - bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CC3S</name>
<description>Capture/Compare 3 selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>C3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4 selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NE</name>
<description>Capture/Compare 2 complementary output enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NE</name>
<description>Capture/Compare 3 complementary output enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 complementary output polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5E</name>
<description>Capture/Compare 5 output enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC5P</name>
<description>Capture/Compare 5 output polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6E</name>
<description>Capture/Compare 6 output enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC6P</name>
<description>Capture/Compare 6 output polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UIFCPY</name>
<description>UIF copy</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR1</name>
<displayName>CCR1</displayName>
<description>capture/compare register 1</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1</name>
<description>Capture/Compare 1 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<displayName>CCR2</displayName>
<description>capture/compare register 2</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR2</name>
<description>Capture/Compare 2 value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR3</name>
<displayName>CCR3</displayName>
<description>capture/compare register 3</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR3</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR4</name>
<displayName>CCR4</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR4</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKF</name>
<description>Break filter</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BK2F</name>
<description>Break 2 filter</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BK2E</name>
<description>Break 2 enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2P</name>
<description>Break 2 polarity</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TIM1_ETR_ADC1_RMP</name>
<description>TIM1_ETR_ADC1 remapping capability</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TI1_RMP</name>
<description>Input Capture 1 remap</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR3_Output</name>
<displayName>CCMR3_Output</displayName>
<description>capture/compare mode register 2 (output mode)</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC6M_bit3</name>
<description>Output Compare 6 mode bit 3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M_bit3</name>
<description>Output Compare 5 mode bit 3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6CE</name>
<description>Output compare 6 clear enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6M</name>
<description>Output compare 6 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC6PE</name>
<description>Output compare 6 preload enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC6FE</name>
<description>Output compare 6 fast enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5CE</name>
<description>Output compare 5 clear enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5M</name>
<description>Output compare 5 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>OC5PE</name>
<description>Output compare 5 preload enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC5FE</name>
<description>Output compare 5 fast enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR5</name>
<displayName>CCR5</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR5</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>GC5C1</name>
<description>Group Channel 5 and Channel 1</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C2</name>
<description>Group Channel 5 and Channel 2</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GC5C3</name>
<description>Group Channel 5 and Channel 3</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR6</name>
<displayName>CCR6</displayName>
<description>capture/compare register 4</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR6</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF1</name>
<displayName>AF1</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>BKINE</name>
<description>BRK BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1E</name>
<description>BRK COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2E</name>
<description>BRK COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKINP</name>
<description>BRK BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP1P</name>
<description>BRK COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKCMP2P</name>
<description>BRK COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETRSEL</name>
<description>ETR source selection</description>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>AF2</name>
<displayName>AF2</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>BK2INE</name>
<description>BRK2 BKIN input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1E</name>
<description>BRK2 COMP1 enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2E</name>
<description>BRK2 COMP2 enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2DFBK0E</name>
<description>BRK2 DFSDM_BREAK0 enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2INP</name>
<description>BRK2 BKIN input polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP1P</name>
<description>BRK2 COMP1 input polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BK2CMP2P</name>
<description>BRK2 COMP2 input polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LPTIM1</name>
<description>Low power timer</description>
<groupName>LPTIM</groupName>
<baseAddress>0x40007C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LPTIM1</name>
<description>LPtimer 1 global interrupt</description>
<value>47</value>
</interrupt>
<registers>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt and Status Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWN</name>
<description>Counter direction change up to down</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UP</name>
<description>Counter direction change down to up</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROK</name>
<description>Autoreload register update OK</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOK</name>
<description>Compare register update OK</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIG</name>
<description>External trigger edge event</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRM</name>
<description>Autoreload match</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPM</name>
<description>Compare match</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNCF</name>
<description>Direction change to down Clear Flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPCF</name>
<description>Direction change to UP Clear Flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKCF</name>
<description>Autoreload register update OK Clear Flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKCF</name>
<description>Compare register update OK Clear Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGCF</name>
<description>External trigger valid edge Clear Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMCF</name>
<description>Autoreload match Clear Flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMCF</name>
<description>compare match Clear Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOWNIE</name>
<description>Direction change to down Interrupt Enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UPIE</name>
<description>Direction change to UP Interrupt Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARROKIE</name>
<description>Autoreload register update OK Interrupt Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPOKIE</name>
<description>Compare register update OK Interrupt Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTTRIGIE</name>
<description>External trigger valid edge Interrupt Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARRMIE</name>
<description>Autoreload match Interrupt Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMPMIE</name>
<description>Compare match Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>Configuration Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENC</name>
<description>Encoder mode enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTMODE</name>
<description>counter mode enabled</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRELOAD</name>
<description>Registers update mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVPOL</name>
<description>Waveform shape polarity</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAVE</name>
<description>Waveform shape</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMOUT</name>
<description>Timeout enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIGEN</name>
<description>Trigger enable and polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TRIGSEL</name>
<description>Trigger selector</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRESC</name>
<description>Clock prescaler</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TRGFLT</name>
<description>Configurable digital filter for trigger</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKFLT</name>
<description>Configurable digital filter for external clock</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKPOL</name>
<description>Clock Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CKSEL</name>
<description>Clock selector</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RSTARE</name>
<description>Reset after read enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTRST</name>
<description>Counter reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNTSTRT</name>
<description>Timer start in continuous mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SNGSTRT</name>
<description>LPTIM start in single mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENABLE</name>
<description>LPTIM Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMP</name>
<displayName>CMP</displayName>
<description>Compare Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMP</name>
<description>Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>Autoreload Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>Counter Register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>Option Register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OR1</name>
<description>Option register bit 1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OR2</name>
<description>Option register bit 2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="LPTIM1">
<name>LPTIM2</name>
<baseAddress>0x40009400</baseAddress>
<interrupt>
<name>LPTIM2</name>
<description>LPtimer 2 global interrupt</description>
<value>48</value>
</interrupt>
</peripheral>
<peripheral>
<name>USART1</name>
<description>Universal synchronous asynchronous receiver transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40013800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>36</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RXFFIE</name>
<description>RXFIFO Full interrupt enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFEIE</name>
<description>TXFIFO empty interrupt enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFOEN</name>
<description>FIFO mode enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M1</name>
<description>Word length</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBIE</name>
<description>End of Block interrupt enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOIE</name>
<description>Receiver timeout interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT4</name>
<description>Driver Enable assertion time</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT3</name>
<description>DEAT3</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT2</name>
<description>DEAT2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT1</name>
<description>DEAT1</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEAT0</name>
<description>DEAT0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT4</name>
<description>Driver Enable de-assertion time</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT3</name>
<description>DEDT3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT2</name>
<description>DEDT2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT1</name>
<description>DEDT1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEDT0</name>
<description>DEDT0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMIE</name>
<description>Character match interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MME</name>
<description>Mute mode enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>M0</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKE</name>
<description>Receiver wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UESM</name>
<description>USART enable in Stop mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADD4_7</name>
<description>Address of the USART node</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ADD0_3</name>
<description>Address of the USART node</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RTOEN</name>
<description>Receiver timeout enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD1</name>
<description>Auto baud rate mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRMOD0</name>
<description>ABRMOD0</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABREN</name>
<description>Auto baud rate enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSBFIRST</name>
<description>Most significant bit first</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAINV</name>
<description>Binary data inversion</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXINV</name>
<description>TX pin active level inversion</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXINV</name>
<description>RX pin active level inversion</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWAP</name>
<description>Swap TX/RX pins</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDL</name>
<description>LIN break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDM7</name>
<description>7-bit Address Detection/4-bit Address Detection</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIS_NSS</name>
<description>When the DSI_NSS bit is set, the NSS pin input will be ignored</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLVEN</name>
<description>Synchronous Slave mode enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXFTCFG</name>
<description>TXFIFO threshold configuration</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFTIE</name>
<description>RXFIFO threshold interrupt enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFTCFG</name>
<description>Receive FIFO threshold configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TCBGTIE</name>
<description>Tr Complete before guard time, interrupt enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFTIE</name>
<description>threshold interrupt enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUFIE</name>
<description>Wakeup from Stop mode interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUS</name>
<description>Wakeup from Stop mode interrupt flag selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SCARCNT</name>
<description>Smartcard auto-retry count</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DEP</name>
<description>Driver enable polarity selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEM</name>
<description>Driver enable mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDRE</name>
<description>DMA Disable on Reception Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVRDIS</name>
<description>Overrun Disable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ONEBIT</name>
<description>One sample bit method enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRLP</name>
<description>Ir low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IREN</name>
<description>Ir mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BRR</name>
<description>BRR_4_15</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTOR</name>
<displayName>RTOR</displayName>
<description>Receiver timeout register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BLEN</name>
<description>Block Length</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RTO</name>
<description>Receiver timeout value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>RQR</name>
<displayName>RQR</displayName>
<description>Request register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXFRQ</name>
<description>Transmit data flush request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFRQ</name>
<description>Receive data flush request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRQ</name>
<description>Mute mode request</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKRQ</name>
<description>Send break request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRRQ</name>
<description>Auto baud rate request</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt & status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00C0</resetValue>
<fields>
<field>
<name>TXFT</name>
<description>TXFIFO threshold flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFT</name>
<description>RXFIFO threshold flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGT</name>
<description>Transmission complete before guard time flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFF</name>
<description>RXFIFO Full</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFE</name>
<description>TXFIFO Empty</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REACK</name>
<description>REACK</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEACK</name>
<description>TEACK</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUF</name>
<description>WUF</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWU</name>
<description>RWU</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SBKF</name>
<description>SBKF</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMF</name>
<description>CMF</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRF</name>
<description>ABRF</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABRE</name>
<description>ABRE</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDR</name>
<description>SPI slave underrun error flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBF</name>
<description>EOBF</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOF</name>
<description>RTOF</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSIF</name>
<description>CTSIF</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDF</name>
<description>LBDF</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TC</name>
<description>TC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNE</name>
<description>RXNE</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE</name>
<description>IDLE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORE</name>
<description>ORE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NF</name>
<description>NF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt flag clear register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>WUCF</name>
<description>Wakeup from Stop mode clear flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMCF</name>
<description>Character match clear flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDRCF</name>
<description>SPI slave underrun clear flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOBCF</name>
<description>End of block clear flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTOCF</name>
<description>Receiver timeout clear flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSCF</name>
<description>CTS clear flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDCF</name>
<description>LIN break detection clear flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCBGTCF</name>
<description>Transmission complete before Guard time clear flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCCF</name>
<description>Transmission complete clear flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFECF</name>
<description>TXFIFO empty clear flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLECF</name>
<description>Idle line detected clear flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ORECF</name>
<description>Overrun error clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NCF</name>
<description>Noise detected clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECF</name>
<description>Framing error clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PECF</name>
<description>Parity error clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDR</name>
<displayName>RDR</displayName>
<description>Receive data register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RDR</name>
<description>Receive data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDR</name>
<displayName>TDR</displayName>
<description>Transmit data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDR</name>
<description>Transmit data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRESC</name>
<displayName>PRESC</displayName>
<description>Prescaler register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PRESCALER</name>
<description>Clock prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART1">
<name>LPUART1</name>
<baseAddress>0x40008000</baseAddress>
<interrupt>
<name>LPUART1</name>
<description>LPUART1 global interrupt</description>
<value>37</value>
</interrupt>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial peripheral interface/Inter-IC sound</description>
<groupName>SPI</groupName>
<baseAddress>0x40013000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<description>SPI 1 global interrupt</description>
<value>34</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BIDIMODE</name>
<description>Bidirectional data mode enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIDIOE</name>
<description>Output enable in bidirectional mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCEN</name>
<description>Hardware CRC calculation enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRCNEXT</name>
<description>CRC transfer next</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DFF</name>
<description>Data frame format</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXONLY</name>
<description>Receive only</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSM</name>
<description>Software slave management</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSI</name>
<description>Internal slave select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSBFIRST</name>
<description>Frame format</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPE</name>
<description>SPI enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BR</name>
<description>Baud rate control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MSTR</name>
<description>Master selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000700</resetValue>
<fields>
<field>
<name>RXDMAEN</name>
<description>Rx buffer DMA enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXDMAEN</name>
<description>Tx buffer DMA enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SSOE</name>
<description>SS output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NSSP</name>
<description>NSS pulse management</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRF</name>
<description>Frame format</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXNEIE</name>
<description>RX buffer not empty interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXEIE</name>
<description>Tx buffer empty interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRXTH</name>
<description>FIFO reception threshold</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDMA_RX</name>
<description>Last DMA transfer for reception</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LDMA_TX</name>
<description>Last DMA transfer for transmission</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>RXNE</name>
<description>Receive buffer not empty</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXE</name>
<description>Transmit buffer empty</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CRCERR</name>
<description>CRC error flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MODF</name>
<description>Mode fault</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVR</name>
<description>Overrun flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BSY</name>
<description>Busy flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TIFRFE</name>
<description>TI frame format error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FRLVL</name>
<description>FIFO reception level</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FTLVL</name>
<description>FIFO transmission level</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRCPR</name>
<displayName>CRCPR</displayName>
<description>CRC polynomial register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>CRCPOLY</name>
<description>CRC polynomial register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXCRCR</name>
<displayName>RXCRCR</displayName>
<description>RX CRC register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RxCRC</name>
<description>Rx CRC register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TXCRCR</name>
<displayName>TXCRCR</displayName>
<description>TX CRC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TxCRC</name>
<description>Tx CRC register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI2</name>
<baseAddress>0x40003800</baseAddress>
<interrupt>
<name>SPI2</name>
<description>SPI1 global interrupt</description>
<value>35</value>
</interrupt>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Real-time clock</description>
<groupName>RTC</groupName>
<baseAddress>0x40002800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC_TAMP</name>
<description>RTC/TAMP/CSS on LSE through EXTI line 19 interrupt</description>
<value>2</value>
</interrupt>
<interrupt>
<name>RTC_WKUP</name>
<description>RTC wakeup interrupt through EXTI[19]</description>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC_ALARM</name>
<description>RTC Alarms (A and B) interrupt through
AIEC</description>
<value>41</value>
</interrupt>
<registers>
<register>
<name>TR</name>
<displayName>TR</displayName>
<description>time register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>date register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002101</resetValue>
<fields>
<field>
<name>YT</name>
<description>Year tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>YU</name>
<description>Year units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WCKSEL</name>
<description>Wakeup clock selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TSEDGE</name>
<description>Time-stamp event active edge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REFCKON</name>
<description>Reference clock detection enable (50 or 60 Hz)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BYPSHAD</name>
<description>Bypass the shadow registers</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FMT</name>
<description>Hour format</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRAE</name>
<description>Alarm A enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRBE</name>
<description>Alarm B enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUTE</name>
<description>Wakeup timer enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSE</name>
<description>Time stamp enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRAIE</name>
<description>Alarm A interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALRBIE</name>
<description>Alarm B interrupt enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WUTIE</name>
<description>Wakeup timer interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSIE</name>
<description>Time-stamp interrupt enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADD1H</name>
<description>Add 1 hour (summer time change)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUB1H</name>
<description>Subtract 1 hour (winter time change)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Backup</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COSEL</name>
<description>Calibration output selection</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>POL</name>
<description>Output polarity</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSEL</name>
<description>Output selection</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COE</name>
<description>Calibration output enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITSE</name>
<description>timestamp on internal event enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>initialization and status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>ALRAWF</name>
<description>Alarm A write flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ALRBWF</name>
<description>Alarm B write flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>WUTWF</name>
<description>Wakeup timer write flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SHPF</name>
<description>Shift operation pending</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INITS</name>
<description>Initialization status flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RSF</name>
<description>Registers synchronization flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INITF</name>
<description>Initialization flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INIT</name>
<description>Initialization mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALRAF</name>
<description>Alarm A flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALRBF</name>
<description>Alarm B flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WUTF</name>
<description>Wakeup timer flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSF</name>
<description>Time-stamp flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSOVF</name>
<description>Time-stamp overflow flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TAMP1F</name>
<description>Tamper detection flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TAMP2F</name>
<description>RTC_TAMP2 detection flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TAMP3F</name>
<description>RTC_TAMP3 detection flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RECALPF</name>
<description>Recalibration pending Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ITSF</name>
<description>INTERNAL TIME-STAMP FLAG</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRER</name>
<displayName>PRER</displayName>
<description>prescaler register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x007F00FF</resetValue>
<fields>
<field>
<name>PREDIV_A</name>
<description>Asynchronous prescaler factor</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PREDIV_S</name>
<description>Synchronous prescaler factor</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>WUTR</name>
<displayName>WUTR</displayName>
<description>wakeup timer register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>WUT</name>
<description>Wakeup auto-reload value bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMAR</name>
<displayName>ALRMAR</displayName>
<description>alarm A register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MSK4</name>
<description>Alarm A date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK3</name>
<description>Alarm A hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK2</name>
<description>Alarm A minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK1</name>
<description>Alarm A seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMBR</name>
<displayName>ALRMBR</displayName>
<description>alarm B register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MSK4</name>
<description>Alarm B date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK3</name>
<description>Alarm B hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK2</name>
<description>Alarm B minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MSK1</name>
<description>Alarm B seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>WPR</name>
<displayName>WPR</displayName>
<description>write protection register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Write protection key</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SSR</name>
<displayName>SSR</displayName>
<description>sub second register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHIFTR</name>
<displayName>SHIFTR</displayName>
<description>shift control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD1S</name>
<description>Add one second</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUBFS</name>
<description>Subtract a fraction of a second</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSTR</name>
<displayName>TSTR</displayName>
<description>time stamp time register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSDR</name>
<displayName>TSDR</displayName>
<description>time stamp date register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSSSR</name>
<displayName>TSSSR</displayName>
<description>timestamp sub second register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALR</name>
<displayName>CALR</displayName>
<description>calibration register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALP</name>
<description>Increase frequency of RTC by 488.5 ppm</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALW8</name>
<description>Use an 8-second calibration cycle period</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALW16</name>
<description>Use a 16-second calibration cycle period</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALM</name>
<description>Calibration minus</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TAMPCR</name>
<displayName>TAMPCR</displayName>
<description>tamper configuration register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TAMP1E</name>
<description>Tamper 1 detection enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1TRG</name>
<description>Active level for tamper 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPIE</name>
<description>Tamper interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2E</name>
<description>Tamper 2 detection enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2TRG</name>
<description>Active level for tamper 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3E</name>
<description>Tamper 3 detection enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3TRG</name>
<description>Active level for tamper 3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPTS</name>
<description>Activate timestamp on tamper detection event</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPFREQ</name>
<description>Tamper sampling frequency</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TAMPFLT</name>
<description>Tamper filter count</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TAMPPRCH</name>
<description>Tamper precharge duration</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TAMPPUDIS</name>
<description>TAMPER pull-up disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1IE</name>
<description>Tamper 1 interrupt enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1NOERASE</name>
<description>Tamper 1 no erase</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1MF</name>
<description>Tamper 1 mask flag</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2IE</name>
<description>Tamper 2 interrupt enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2NOERASE</name>
<description>Tamper 2 no erase</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2MF</name>
<description>Tamper 2 mask flag</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3IE</name>
<description>Tamper 3 interrupt enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3NOERASE</name>
<description>Tamper 3 no erase</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP3MF</name>
<description>Tamper 3 mask flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMASSR</name>
<displayName>ALRMASSR</displayName>
<description>alarm A sub second register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting at this bit</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SS</name>
<description>Sub seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMBSSR</name>
<displayName>ALRMBSSR</displayName>
<description>alarm B sub second register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting at this bit</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SS</name>
<description>Sub seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>option register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RTC_ALARM_TYPE</name>
<description>RTC_ALARM on PC13 output type</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTC_OUT_RMP</name>
<description>RTC_OUT remap</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP0R</name>
<displayName>BKP0R</displayName>
<description>backup register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP1R</name>
<displayName>BKP1R</displayName>
<description>backup register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP2R</name>
<displayName>BKP2R</displayName>
<description>backup register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP3R</name>
<displayName>BKP3R</displayName>
<description>backup register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP4R</name>
<displayName>BKP4R</displayName>
<description>backup register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP5R</name>
<displayName>BKP5R</displayName>
<description>backup register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP6R</name>
<displayName>BKP6R</displayName>
<description>backup register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP7R</name>
<displayName>BKP7R</displayName>
<description>backup register</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP8R</name>
<displayName>BKP8R</displayName>
<description>backup register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP9R</name>
<displayName>BKP9R</displayName>
<description>backup register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP10R</name>
<displayName>BKP10R</displayName>
<description>backup register</description>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP11R</name>
<displayName>BKP11R</displayName>
<description>backup register</description>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP12R</name>
<displayName>BKP12R</displayName>
<description>backup register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP13R</name>
<displayName>BKP13R</displayName>
<description>backup register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP14R</name>
<displayName>BKP14R</displayName>
<description>backup register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP15R</name>
<displayName>BKP15R</displayName>
<description>backup register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP16R</name>
<displayName>BKP16R</displayName>
<description>backup register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP17R</name>
<displayName>BKP17R</displayName>
<description>backup register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP18R</name>
<displayName>BKP18R</displayName>
<description>backup register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BKP19R</name>
<displayName>BKP19R</displayName>
<description>backup register</description>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DBGMCU</name>
<description>Debug support</description>
<groupName>DBGMCU</groupName>
<baseAddress>0xE0042000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IDCODE</name>
<displayName>IDCODE</displayName>
<description>MCU Device ID Code Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DEV_ID</name>
<description>Device Identifier</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>REV_ID</name>
<description>Revision Identifier</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Debug MCU Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_SLEEP</name>
<description>Debug Sleep Mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_STOP</name>
<description>Debug Stop Mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_STANDBY</name>
<description>Debug Standby Mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACE_IOEN</name>
<description>Trace port and clock enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRGOEN</name>
<description>External trigger output enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1FZR1</name>
<displayName>APB1FZR1</displayName>
<description>APB1 Low Freeze Register CPU1</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_TIMER2_STOP</name>
<description>Debug Timer 2 stopped when Core is halted</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_RTC_STOP</name>
<description>RTC counter stopped when core is halted</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_WWDG_STOP</name>
<description>WWDG counter stopped when core is halted</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_IWDG_STOP</name>
<description>IWDG counter stopped when core is halted</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C1_STOP</name>
<description>Debug I2C1 SMBUS timeout stopped when Core is halted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C3_STOP</name>
<description>Debug I2C3 SMBUS timeout stopped when core is halted</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_LPTIM1_STOP</name>
<description>Debug LPTIM1 stopped when Core is halted</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2AP_B1FZR1</name>
<displayName>C2AP_B1FZR1</displayName>
<description>APB1 Low Freeze Register CPU2</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_LPTIM2_STOP</name>
<description>LPTIM2 counter stopped when core is halted</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_RTC_STOP</name>
<description>RTC counter stopped when core is halted</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_IWDG_STOP</name>
<description>IWDG stopped when core is halted</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C1_STOP</name>
<description>I2C1 SMBUS timeout stopped when core is halted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_I2C3_STOP</name>
<description>I2C3 SMBUS timeout stopped when core is halted</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_LPTIM1_STOP</name>
<description>LPTIM1 counter stopped when core is halted</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1FZR2</name>
<displayName>APB1FZR2</displayName>
<description>APB1 High Freeze Register CPU1</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_LPTIM2_STOP</name>
<description>LPTIM2 counter stopped when core is halted</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB1FZR2</name>
<displayName>C2APB1FZR2</displayName>
<description>APB1 High Freeze Register CPU2</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_LPTIM2_STOP</name>
<description>LPTIM2 counter stopped when core is halted</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2FZR</name>
<displayName>APB2FZR</displayName>
<description>APB2 Freeze Register CPU1</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_TIM1_STOP</name>
<description>TIM1 counter stopped when core is halted</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM16_STOP</name>
<description>TIM16 counter stopped when core is halted</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM17_STOP</name>
<description>TIM17 counter stopped when core is halted</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2APB2FZR</name>
<displayName>C2APB2FZR</displayName>
<description>APB2 Freeze Register CPU2</description>
<alternateRegister>C2APB1FZR2</alternateRegister>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DBG_TIM1_STOP</name>
<description>TIM1 counter stopped when core is halted</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM16_STOP</name>
<description>TIM16 counter stopped when core is halted</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM17_STOP</name>
<description>TIM17 counter stopped when core is halted</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PKA</name>
<description>PKA</description>
<groupName>PKA</groupName>
<baseAddress>0x58002000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x2000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PKA</name>
<description>Private key accelerator
interrupt</description>
<value>29</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRERRIE</name>
<description>Address error interrupt enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RAMERRIE</name>
<description>RAM error interrupt enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PROCENDIE</name>
<description>End of operation interrupt enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MODE</name>
<description>PKA Operation Mode</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SECLVL</name>
<description>Security Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start the operation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EN</name>
<description>Peripheral Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>PKA status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRERRF</name>
<description>Address error flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RAMERRF</name>
<description>RAM error flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PROCENDF</name>
<description>PKA End of Operation flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>PKA Operation in progress</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLRFR</name>
<displayName>CLRFR</displayName>
<description>PKA clear flag register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRERRFC</name>
<description>Clear Address error flag</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RAMERRFC</name>
<description>Clear RAM error flag</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PROCENDFC</name>
<description>Clear PKA End of Operation flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>PKA version register</description>
<addressOffset>0x1FF4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>MINREV</name>
<description>Minor revision</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MAJREV</name>
<description>Major revision</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPIDR</name>
<displayName>IPIDR</displayName>
<description>PKA identification register</description>
<addressOffset>0x1FF8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00170061</resetValue>
<fields>
<field>
<name>ID</name>
<description>Identification Code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>PKA size ID register</description>
<addressOffset>0x1FFC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD08</resetValue>
<fields>
<field>
<name>SID</name>
<description>Side Identification Code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IPCC</name>
<description>IPCC</description>
<groupName>IPCC</groupName>
<baseAddress>0x58000C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>IPCC_C1_RX_IT</name>
<description>IPCC CPU1 RX occupied interrupt</description>
<value>44</value>
</interrupt>
<interrupt>
<name>IPCC_C1_TX_IT</name>
<description>IPCC CPU1 TX free interrupt</description>
<value>45</value>
</interrupt>
<registers>
<register>
<name>C1CR</name>
<displayName>C1CR</displayName>
<description>Control register CPU1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFIE</name>
<description>processor 1 Transmit channel free interrupt enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOIE</name>
<description>processor 1 Receive channel occupied interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1MR</name>
<displayName>C1MR</displayName>
<description>Mask register CPU1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>CH6FM</name>
<description>processor 1 Transmit channel 6 free interrupt mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5FM</name>
<description>processor 1 Transmit channel 5 free interrupt mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4FM</name>
<description>processor 1 Transmit channel 4 free interrupt mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3FM</name>
<description>processor 1 Transmit channel 3 free interrupt mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2FM</name>
<description>processor 1 Transmit channel 2 free interrupt mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1FM</name>
<description>processor 1 Transmit channel 1 free interrupt mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6OM</name>
<description>processor 1 Receive channel 6 occupied interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5OM</name>
<description>processor 1 Receive channel 5 occupied interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4OM</name>
<description>processor 1 Receive channel 4 occupied interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3OM</name>
<description>processor 1 Receive channel 3 occupied interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2OM</name>
<description>processor 1 Receive channel 2 occupied interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1OM</name>
<description>processor 1 Receive channel 1 occupied interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1SCR</name>
<displayName>C1SCR</displayName>
<description>Status Set or Clear register CPU1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH6S</name>
<description>processor 1 Transmit channel 6 status set</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5S</name>
<description>processor 1 Transmit channel 5 status set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4S</name>
<description>processor 1 Transmit channel 4 status set</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3S</name>
<description>processor 1 Transmit channel 3 status set</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2S</name>
<description>processor 1 Transmit channel 2 status set</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1S</name>
<description>processor 1 Transmit channel 1 status set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6C</name>
<description>processor 1 Receive channel 6 status clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5C</name>
<description>processor 1 Receive channel 5 status clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4C</name>
<description>processor 1 Receive channel 4 status clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3C</name>
<description>processor 1 Receive channel 3 status clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2C</name>
<description>processor 1 Receive channel 2 status clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1C</name>
<description>processor 1 Receive channel 1 status clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1TO2SR</name>
<displayName>C1TO2SR</displayName>
<description>CPU1 to CPU2 status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH6F</name>
<description>processor 1 transmit to process 2 Receive channel 6 status flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5F</name>
<description>processor 1 transmit to process 2 Receive channel 5 status flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4F</name>
<description>processor 1 transmit to process 2 Receive channel 4 status flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3F</name>
<description>processor 1 transmit to process 2 Receive channel 3 status flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2F</name>
<description>processor 1 transmit to process 2 Receive channel 2 status flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1F</name>
<description>processor 1 transmit to process 2 Receive channel 1 status flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2CR</name>
<displayName>C2CR</displayName>
<description>Control register CPU2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFIE</name>
<description>processor 2 Transmit channel free interrupt enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXOIE</name>
<description>processor 2 Receive channel occupied interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2MR</name>
<displayName>C2MR</displayName>
<description>Mask register CPU2</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>CH6FM</name>
<description>processor 2 Transmit channel 6 free interrupt mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5FM</name>
<description>processor 2 Transmit channel 5 free interrupt mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4FM</name>
<description>processor 2 Transmit channel 4 free interrupt mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3FM</name>
<description>processor 2 Transmit channel 3 free interrupt mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2FM</name>
<description>processor 2 Transmit channel 2 free interrupt mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1FM</name>
<description>processor 2 Transmit channel 1 free interrupt mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6OM</name>
<description>processor 2 Receive channel 6 occupied interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5OM</name>
<description>processor 2 Receive channel 5 occupied interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4OM</name>
<description>processor 2 Receive channel 4 occupied interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3OM</name>
<description>processor 2 Receive channel 3 occupied interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2OM</name>
<description>processor 2 Receive channel 2 occupied interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1OM</name>
<description>processor 2 Receive channel 1 occupied interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2SCR</name>
<displayName>C2SCR</displayName>
<description>Status Set or Clear register CPU2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH6S</name>
<description>processor 2 Transmit channel 6 status set</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5S</name>
<description>processor 2 Transmit channel 5 status set</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4S</name>
<description>processor 2 Transmit channel 4 status set</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3S</name>
<description>processor 2 Transmit channel 3 status set</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2S</name>
<description>processor 2 Transmit channel 2 status set</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1S</name>
<description>processor 2 Transmit channel 1 status set</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6C</name>
<description>processor 2 Receive channel 6 status clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5C</name>
<description>processor 2 Receive channel 5 status clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4C</name>
<description>processor 2 Receive channel 4 status clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3C</name>
<description>processor 2 Receive channel 3 status clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2C</name>
<description>processor 2 Receive channel 2 status clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1C</name>
<description>processor 2 Receive channel 1 status clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2TOC1SR</name>
<displayName>C2TOC1SR</displayName>
<description>CPU2 to CPU1 status register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH6F</name>
<description>processor 2 transmit to process 1 Receive channel 6 status flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5F</name>
<description>processor 2 transmit to process 1 Receive channel 5 status flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4F</name>
<description>processor 2 transmit to process 1 Receive channel 4 status flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3F</name>
<description>processor 2 transmit to process 1 Receive channel 3 status flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2F</name>
<description>processor 2 transmit to process 1 Receive channel 2 status flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1F</name>
<description>processor 2 transmit to process 1 Receive channel 1 status flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR</name>
<displayName>HWCFGR</displayName>
<description>IPCC Hardware configuration register</description>
<addressOffset>0x3F0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000006</resetValue>
<fields>
<field>
<name>CHANNELS</name>
<description>Number of channels per CPU supported by the IP, range 1 to 16</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>IPCC version register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>MAJREV</name>
<description>Major Revision</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MINREV</name>
<description>Minor Revision</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPIDR</name>
<displayName>IPIDR</displayName>
<description>IPCC indentification register</description>
<addressOffset>0x3F8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00100071</resetValue>
<fields>
<field>
<name>IPID</name>
<description>Identification Code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>IPCC size indentification register</description>
<addressOffset>0x3FC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD01</resetValue>
<fields>
<field>
<name>SID</name>
<description>Size Identification Code</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EXTI</name>
<description>External interrupt/event controller</description>
<groupName>EXTI</groupName>
<baseAddress>0x58000800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PVD</name>
<description>PVD through EXTI[16] (C1IMR2[20])</description>
<value>1</value>
</interrupt>
<interrupt>
<name>EXTI0</name>
<description>EXTI line 0 interrupt through
EXTI[0]</description>
<value>6</value>
</interrupt>
<interrupt>
<name>EXTI1</name>
<description>EXTI line 0 interrupt through
EXTI[1]</description>
<value>7</value>
</interrupt>
<interrupt>
<name>EXTI2</name>
<description>EXTI line 0 interrupt through
EXTI[2]</description>
<value>8</value>
</interrupt>
<interrupt>
<name>EXTI3</name>
<description>EXTI line 0 interrupt through
EXTI[3]</description>
<value>9</value>
</interrupt>
<interrupt>
<name>EXTI4</name>
<description>EXTI line 0 interrupt through
EXTI[4]</description>
<value>10</value>
</interrupt>
<interrupt>
<name>C2SEV</name>
<description>CPU2 SEV through EXTI[40]</description>
<value>21</value>
</interrupt>
<interrupt>
<name>EXTI5_9</name>
<description>EXTI line [9:5] interrupt through
EXTI[9:5]</description>
<value>23</value>
</interrupt>
<interrupt>
<name>EXTI10_15</name>
<description>EXTI line [15:10] interrupt through
EXTI[15:10]</description>
<value>40</value>
</interrupt>
<registers>
<register>
<name>RTSR1</name>
<displayName>RTSR1</displayName>
<description>rising trigger selection register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RT</name>
<description>Rising trigger event configuration bit of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
<field>
<name>RT_31</name>
<description>Rising trigger event configuration bit of Configurable Event input</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR1</name>
<displayName>FTSR1</displayName>
<description>falling trigger selection register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FT</name>
<description>Falling trigger event configuration bit of Configurable Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
<field>
<name>FT_31</name>
<description>Falling trigger event configuration bit of Configurable Event input</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER1</name>
<displayName>SWIER1</displayName>
<description>software interrupt event register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWI</name>
<description>Software interrupt on event</description>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
<field>
<name>SWI_31</name>
<description>Software interrupt on event</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR1</name>
<displayName>PR1</displayName>
<description>EXTI pending register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PIF</name>
<description>Configurable event inputs Pending bit</description>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
<field>
<name>PIF_31</name>
<description>Configurable event inputs Pending bit</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTSR2</name>
<displayName>RTSR2</displayName>
<description>rising trigger selection register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RT33</name>
<description>Rising trigger event configuration bit of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RT40_41</name>
<description>Rising trigger event configuration bit of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FTSR2</name>
<displayName>FTSR2</displayName>
<description>falling trigger selection register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FT33</name>
<description>Falling trigger event configuration bit of Configurable Event input</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FT40_41</name>
<description>Falling trigger event configuration bit of Configurable Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWIER2</name>
<displayName>SWIER2</displayName>
<description>software interrupt event register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWI33</name>
<description>Software interrupt on event</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWI40_41</name>
<description>Software interrupt on event</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PR2</name>
<displayName>PR2</displayName>
<description>pending register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PIF33</name>
<description>Configurable event inputs x+32 Pending bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIF40_41</name>
<description>Configurable event inputs x+32 Pending bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1IMR1</name>
<displayName>C1IMR1</displayName>
<description>CPUm wakeup with interrupt mask register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7FC00000</resetValue>
<fields>
<field>
<name>IM</name>
<description>CPU(m) wakeup with interrupt Mask on Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2IMR1</name>
<displayName>C2IMR1</displayName>
<description>CPUm wakeup with interrupt mask register</description>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7FC00000</resetValue>
<fields>
<field>
<name>IM</name>
<description>CPU(m) wakeup with interrupt Mask on Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1EMR1</name>
<displayName>C1EMR1</displayName>
<description>CPUm wakeup with event mask register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM0_15</name>
<description>CPU(m) Wakeup with event generation Mask on Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>EM17_21</name>
<description>CPU(m) Wakeup with event generation Mask on Event input</description>
<bitOffset>17</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2EMR1</name>
<displayName>C2EMR1</displayName>
<description>CPUm wakeup with event mask register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM0_15</name>
<description>CPU(m) Wakeup with event generation Mask on Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>EM17_21</name>
<description>CPU(m) Wakeup with event generation Mask on Event input</description>
<bitOffset>17</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1IMR2</name>
<displayName>C1IMR2</displayName>
<description>CPUm wakeup with interrupt mask register</description>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0001FCFD</resetValue>
<fields>
<field>
<name>IM</name>
<description>CPUm Wakeup with interrupt Mask on Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2IMR2</name>
<displayName>C2IMR2</displayName>
<description>CPUm wakeup with interrupt mask register</description>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0001FCFD</resetValue>
<fields>
<field>
<name>IM</name>
<description>CPUm Wakeup with interrupt Mask on Event input</description>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
</fields>
</register>
<register>
<name>C1EMR2</name>
<displayName>C1EMR2</displayName>
<description>CPUm wakeup with event mask register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM</name>
<description>CPU(m) Wakeup with event generation Mask on Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>C2EMR2</name>
<displayName>C2EMR2</displayName>
<description>CPUm wakeup with event mask register</description>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EM</name>
<description>CPU(m) Wakeup with event generation Mask on Event input</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR5</name>
<displayName>HWCFGR5</displayName>
<description>Hardware configuration registers</description>
<addressOffset>0x3E0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x003EFFFF</resetValue>
<fields>
<field>
<name>CPUEVENT</name>
<description>HW configuration CPU event generation</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR6</name>
<displayName>HWCFGR6</displayName>
<description>Hardware configuration registers</description>
<addressOffset>0x3DC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000300</resetValue>
<fields>
<field>
<name>CPUEVENT</name>
<description>HW configuration CPU event generation</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR7</name>
<displayName>HWCFGR7</displayName>
<description>EXTI Hardware configuration registers</description>
<addressOffset>0x3D8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPUEVENT</name>
<description>HW configuration CPU event generation</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR2</name>
<displayName>HWCFGR2</displayName>
<description>Hardware configuration registers</description>
<addressOffset>0x3EC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x803FFFFF</resetValue>
<fields>
<field>
<name>EVENT_TRG</name>
<description>HW configuration event trigger type</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR3</name>
<displayName>HWCFGR3</displayName>
<description>Hardware configuration registers</description>
<addressOffset>0x3E8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000302</resetValue>
<fields>
<field>
<name>EVENT_TRG</name>
<description>HW configuration event trigger type</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR4</name>
<displayName>HWCFGR4</displayName>
<description>Hardware configuration registers</description>
<addressOffset>0x3E4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EVENT_TRG</name>
<description>HW configuration event trigger type</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HWCFGR1</name>
<displayName>HWCFGR1</displayName>
<description>Hardware configuration register 1</description>
<addressOffset>0x3F0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00003130</resetValue>
<fields>
<field>
<name>NBEVENTS</name>
<description>HW configuration number of event</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NBCPUS</name>
<description>HW configuration number of CPUs</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CPUEVTEN</name>
<description>HW configuration of CPU(m) event output enable</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERR</name>
<displayName>VERR</displayName>
<description>EXTI IP Version register</description>
<addressOffset>0x3F4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000020</resetValue>
<fields>
<field>
<name>MINREV</name>
<description>Minor Revision number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MAJREV</name>
<description>Major Revision number</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPIDR</name>
<displayName>IPIDR</displayName>
<description>Identification register</description>
<addressOffset>0x3F8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x000E0001</resetValue>
<fields>
<field>
<name>IPID</name>
<description>IP Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIDR</name>
<displayName>SIDR</displayName>
<description>Size ID register</description>
<addressOffset>0x3FC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0xA3C5DD01</resetValue>
<fields>
<field>
<name>SID</name>
<description>Size Identification</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRS</name>
<description>Clock recovery system</description>
<groupName>CRS</groupName>
<baseAddress>0x40006000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRS_IT</name>
<description>CRS interrupt</description>
<value>42</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>CRS control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002000</resetValue>
<fields>
<field>
<name>SYNCOKIE</name>
<description>SYNC event OK interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNIE</name>
<description>SYNC warning interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRIE</name>
<description>Synchronization or trimming error interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCIE</name>
<description>Expected SYNC interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CEN</name>
<description>Frequency error counter enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AUTOTRIMEN</name>
<description>Automatic trimming enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWSYNC</name>
<description>Automatic trimming enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIM</name>
<description>HSI48 oscillator smooth trimming</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>CRS configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x2022BB7F</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>Counter reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FELIM</name>
<description>Frequency error limit</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SYNCDIV</name>
<description>SYNCDIV</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SYNCSRC</name>
<description>SYNC signal source selection</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SYNCPOL</name>
<description>SYNC polarity selection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>CRS interrupt and status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKF</name>
<description>SYNC event OK flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNF</name>
<description>SYNC warning flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRF</name>
<description>Error flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCF</name>
<description>Expected SYNC flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCERR</name>
<description>SYNC error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCMISS</name>
<description>SYNC missed</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRIMOVF</name>
<description>Trimming overflow or underflow</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FEDIR</name>
<description>Frequency error direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FECAP</name>
<description>Frequency error capture</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>CRS interrupt flag clear register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNCOKC</name>
<description>SYNC event OK clear flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYNCWARNC</name>
<description>warning clear flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRC</name>
<description>Error clear flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESYNCC</name>
<description>Expected SYNC clear flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USB</name>
<description>Universal serial bus full-speed device interface</description>
<groupName>USB</groupName>
<baseAddress>0x40006800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x800</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USB_HP</name>
<description>USB high priority interrupt</description>
<value>19</value>
</interrupt>
<interrupt>
<name>USB_LP</name>
<description>USB low priority interrupt (including USB
wakeup)</description>
<value>20</value>
</interrupt>
<registers>
<register>
<name>EP0R</name>
<displayName>EP0R</displayName>
<description>endpoint 0 register</description>
<addressOffset>0x0</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP1R</name>
<displayName>EP1R</displayName>
<description>endpoint 1 register</description>
<addressOffset>0x4</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP2R</name>
<displayName>EP2R</displayName>
<description>endpoint 2 register</description>
<addressOffset>0x8</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP3R</name>
<displayName>EP3R</displayName>
<description>endpoint 3 register</description>
<addressOffset>0xC</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP4R</name>
<displayName>EP4R</displayName>
<description>endpoint 4 register</description>
<addressOffset>0x10</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP5R</name>
<displayName>EP5R</displayName>
<description>endpoint 5 register</description>
<addressOffset>0x14</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP6R</name>
<displayName>EP6R</displayName>
<description>endpoint 6 register</description>
<addressOffset>0x18</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EP7R</name>
<displayName>EP7R</displayName>
<description>endpoint 7 register</description>
<addressOffset>0x1C</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EA</name>
<description>Endpoint address</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>STAT_TX</name>
<description>Status bits, for transmission transfers</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_TX</name>
<description>Data Toggle, for transmission transfers</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_TX</name>
<description>Correct Transfer for transmission</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_KIND</name>
<description>Endpoint kind</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EP_TYPE</name>
<description>Endpoint type</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SETUP</name>
<description>Setup transaction completed</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STAT_RX</name>
<description>Status bits, for reception transfers</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTOG_RX</name>
<description>Data Toggle, for reception transfers</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTR_RX</name>
<description>Correct transfer for reception</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTR</name>
<displayName>CNTR</displayName>
<description>control register</description>
<addressOffset>0x40</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x00000003</resetValue>
<fields>
<field>
<name>FRES</name>
<description>Force USB Reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDWN</name>
<description>Power down</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPMODE</name>
<description>Low-power mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSUSP</name>
<description>Force suspend</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESUME</name>
<description>Resume request</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>L1RESUME</name>
<description>LPM L1 Resume request</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>L1REQM</name>
<description>LPM L1 state request interrupt mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESOFM</name>
<description>Expected start of frame interrupt mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFM</name>
<description>Start of frame interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESETM</name>
<description>USB reset interrupt mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSPM</name>
<description>Suspend mode interrupt mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WKUPM</name>
<description>Wakeup interrupt mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERRM</name>
<description>Error interrupt mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PMAOVRM</name>
<description>Packet memory area over / underrun interrupt mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTRM</name>
<description>Correct transfer interrupt mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISTR</name>
<displayName>ISTR</displayName>
<description>interrupt status register</description>
<addressOffset>0x44</addressOffset>
<size>0x10</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EP_ID</name>
<description>Endpoint Identifier</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DIR</name>
<description>Direction of transaction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>L1REQ</name>
<description>LPM L1 state request</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESOF</name>
<description>Expected start frame</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOF</name>
<description>start of frame</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RESET</name>
<description>reset request</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SUSP</name>
<description>Suspend mode request</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WKUP</name>
<description>Wakeup</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERR</name>
<description>Error</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PMAOVR</name>
<description>Packet memory area over / underrun</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTR</name>
<description>Correct transfer</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FNR</name>
<displayName>FNR</displayName>
<description>frame number register</description>
<addressOffset>0x48</addressOffset>
<size>0x10</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FN</name>
<description>Frame number</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>LSOF</name>
<description>Lost SOF</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>LCK</name>
<description>Locked</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDM</name>
<description>Receive data - line status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXDP</name>
<description>Receive data + line status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DADDR</name>
<displayName>DADDR</displayName>
<description>device address</description>
<addressOffset>0x4C</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADD</name>
<description>Device address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>EF</name>
<description>Enable function</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BTABLE</name>
<displayName>BTABLE</displayName>
<description>Buffer table address</description>
<addressOffset>0x50</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BTABLE</name>
<description>Buffer table</description>
<bitOffset>3</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT0_TX</name>
<displayName>COUNT0_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x52</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT0_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT1_TX</name>
<displayName>COUNT1_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x5A</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT1_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT2_TX</name>
<displayName>COUNT2_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x62</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT2_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT3_TX</name>
<displayName>COUNT3_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x6A</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT3_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT4_TX</name>
<displayName>COUNT4_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x72</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT4_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT5_TX</name>
<displayName>COUNT5_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x7A</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT5_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT6_TX</name>
<displayName>COUNT6_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x82</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT6_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT7_TX</name>
<displayName>COUNT7_TX</displayName>
<description>Transmission byte count 0</description>
<addressOffset>0x8A</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT7_TX</name>
<description>Transmission byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR0_RX</name>
<displayName>ADDR0_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x54</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR0_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR1_RX</name>
<displayName>ADDR1_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x5C</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR1_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR2_RX</name>
<displayName>ADDR2_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x64</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR2_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR3_RX</name>
<displayName>ADDR3_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x6C</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR3_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR4_RX</name>
<displayName>ADDR4_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x74</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR4_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR5_RX</name>
<displayName>ADDR5_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x7C</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR5_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR6_RX</name>
<displayName>ADDR6_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x84</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR6_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADDR7_RX</name>
<displayName>ADDR7_RX</displayName>
<description>Reception buffer address 0</description>
<addressOffset>0x8C</addressOffset>
<size>0x10</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDR7_RX</name>
<description>Reception buffer address</description>
<bitOffset>1</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>COUNT0_RX</name>
<displayName>COUNT0_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x56</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT0_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT1_RX</name>
<displayName>COUNT1_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x5E</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT1_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT2_RX</name>
<displayName>COUNT2_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x66</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT2_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT3_RX</name>
<displayName>COUNT3_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x6E</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT3_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT4_RX</name>
<displayName>COUNT4_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x76</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT4_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT5_RX</name>
<displayName>COUNT5_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x7E</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT5_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT6_RX</name>
<displayName>COUNT6_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x86</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT6_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNT7_RX</name>
<displayName>COUNT7_RX</displayName>
<description>Reception byte count 0</description>
<addressOffset>0x8E</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>COUNT7_RX</name>
<description>Reception byte count</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NUM_BLOCK</name>
<description>Number of blocks</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BL_SIZE</name>
<description>Block size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LPMCSR</name>
<displayName>LPMCSR</displayName>
<description>control and status register</description>
<alternateRegister>ADDR0_RX</alternateRegister>
<addressOffset>0x54</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LPMEN</name>
<description>LPM support enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPMACK</name>
<description>LPM Token acknowledge enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>REMWAKE</name>
<description>RemoteWake value</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BESL</name>
<description>BESL value</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BCDR</name>
<displayName>BCDR</displayName>
<description>Battery charging detector(</description>
<addressOffset>0x58</addressOffset>
<size>0x10</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BCDEN</name>
<description>Battery charging detector (BCD) enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DCDEN</name>
<description>Data contact detection (DCD) mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PDEN</name>
<description>Primary detection (PD) mode enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDEN</name>
<description>Secondary detection (SD) mode enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DCDET</name>
<description>Data contact detection (DCD) status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PDET</name>
<description>Primary detection (PD) status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SDET</name>
<description>Secondary detection (SD) status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PS2DET</name>
<description>DM pull-up detection status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DPPU</name>
<description>DP pull-up control</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB</name>
<description>System control block</description>
<groupName>SCB</groupName>
<baseAddress>0xE000ED00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x41</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPUID</name>
<displayName>CPUID</displayName>
<description>CPUID base register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x410FC241</resetValue>
<fields>
<field>
<name>Revision</name>
<description>Revision number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PartNo</name>
<description>Part number of the processor</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>Constant</name>
<description>Reads as 0xF</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Variant</name>
<description>Variant number</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Implementer</name>
<description>Implementer code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<displayName>ICSR</displayName>
<description>Interrupt control and state register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTACTIVE</name>
<description>Active vector</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RETTOBASE</name>
<description>Return to base level</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTPENDING</name>
<description>Pending vector</description>
<bitOffset>12</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ISRPENDING</name>
<description>Interrupt pending flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTCLR</name>
<description>SysTick exception clear-pending bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTSET</name>
<description>SysTick exception set-pending bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVCLR</name>
<description>PendSV clear-pending bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVSET</name>
<description>PendSV set-pending bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NMIPENDSET</name>
<description>NMI set-pending bit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VTOR</name>
<displayName>VTOR</displayName>
<description>Vector table offset register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBLOFF</name>
<description>Vector table base offset field</description>
<bitOffset>9</bitOffset>
<bitWidth>21</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIRCR</name>
<displayName>AIRCR</displayName>
<description>Application interrupt and reset control register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTRESET</name>
<description>VECTRESET</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTCLRACTIVE</name>
<description>VECTCLRACTIVE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSRESETREQ</name>
<description>SYSRESETREQ</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIGROUP</name>
<description>PRIGROUP</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ENDIANESS</name>
<description>ENDIANESS</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>System control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEPONEXIT</name>
<description>SLEEPONEXIT</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLEEPDEEP</name>
<description>SLEEPDEEP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEVEONPEND</name>
<description>Send Event on Pending bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>Configuration and control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NONBASETHRDENA</name>
<description>Configures how the processor enters Thread mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USERSETMPEND</name>
<description>USERSETMPEND</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGN__TRP</name>
<description>UNALIGN_ TRP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_0_TRP</name>
<description>DIV_0_TRP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFHFNMIGN</name>
<description>BFHFNMIGN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKALIGN</name>
<description>STKALIGN</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR1</name>
<displayName>SHPR1</displayName>
<description>System handler priority registers</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_4</name>
<description>Priority of system handler 4</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_5</name>
<description>Priority of system handler 5</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_6</name>
<description>Priority of system handler 6</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR2</name>
<displayName>SHPR2</displayName>
<description>System handler priority registers</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_11</name>
<description>Priority of system handler 11</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR3</name>
<displayName>SHPR3</displayName>
<description>System handler priority registers</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_14</name>
<description>Priority of system handler 14</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_15</name>
<description>Priority of system handler 15</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHCSR</name>
<displayName>SHCSR</displayName>
<description>System handler control and state register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEMFAULTACT</name>
<description>Memory management fault exception active bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTACT</name>
<description>Bus fault exception active bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTACT</name>
<description>Usage fault exception active bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLACT</name>
<description>SVC call active bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONITORACT</name>
<description>Debug monitor active bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVACT</name>
<description>PendSV exception active bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSTICKACT</name>
<description>SysTick exception active bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTPENDED</name>
<description>Usage fault exception pending bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTPENDED</name>
<description>Memory management fault exception pending bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTPENDED</name>
<description>Bus fault exception pending bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLPENDED</name>
<description>SVC call pending bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTENA</name>
<description>Memory management fault enable bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTENA</name>
<description>Bus fault enable bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTENA</name>
<description>Usage fault enable bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFSR_UFSR_BFSR_MMFSR</name>
<displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
<description>Configurable fault status register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IACCVIOL</name>
<description>Instruction access violation flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUNSTKERR</name>
<description>Memory manager fault on unstacking for a return from exception</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTKERR</name>
<description>Memory manager fault on stacking for exception entry.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MLSPERR</name>
<description>MLSPERR</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMARVALID</name>
<description>Memory Management Fault Address Register (MMAR) valid flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IBUSERR</name>
<description>Instruction bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRECISERR</name>
<description>Precise data bus error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IMPRECISERR</name>
<description>Imprecise data bus error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNSTKERR</name>
<description>Bus fault on unstacking for a return from exception</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKERR</name>
<description>Bus fault on stacking for exception entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPERR</name>
<description>Bus fault on floating-point lazy state preservation</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFARVALID</name>
<description>Bus Fault Address Register (BFAR) valid flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDEFINSTR</name>
<description>Undefined instruction usage fault</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVSTATE</name>
<description>Invalid state usage fault</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVPC</name>
<description>Invalid PC load usage fault</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOCP</name>
<description>No coprocessor usage fault.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGNED</name>
<description>Unaligned access usage fault</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIVBYZERO</name>
<description>Divide by zero usage fault</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HFSR</name>
<displayName>HFSR</displayName>
<description>Hard fault status register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTTBL</name>
<description>Vector table hard fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCED</name>
<description>Forced hard fault</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBUG_VT</name>
<description>Reserved for Debug use</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMFAR</name>
<displayName>MMFAR</displayName>
<description>Memory management fault address register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMFAR</name>
<description>Memory management fault address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFAR</name>
<displayName>BFAR</displayName>
<description>Bus fault address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BFAR</name>
<description>Bus fault address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFSR</name>
<displayName>AFSR</displayName>
<description>Auxiliary fault status register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMPDEF</name>
<description>Implementation defined</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>STK</name>
<description>SysTick timer</description>
<groupName>STK</groupName>
<baseAddress>0xE000E010</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x11</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>SysTick control and status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICKINT</name>
<description>SysTick exception request enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSOURCE</name>
<description>Clock source selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTFLAG</name>
<description>COUNTFLAG</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<displayName>LOAD</displayName>
<description>SysTick reload value register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>RELOAD value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>VAL</name>
<displayName>VAL</displayName>
<description>SysTick current value register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>CURRENT</name>
<description>Current counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALIB</name>
<displayName>CALIB</displayName>
<description>SysTick calibration value register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>TENMS</name>
<description>Calibration value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>SKEW</name>
<description>SKEW flag: Indicates whether the TENMS value is exact</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOREF</name>
<description>NOREF flag. Reads as zero</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MPU</name>
<description>Memory protection unit</description>
<groupName>MPU</groupName>
<baseAddress>0xE000ED90</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x15</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MPU_TYPER</name>
<displayName>MPU_TYPER</displayName>
<description>MPU type register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000800</resetValue>
<fields>
<field>
<name>SEPARATE</name>
<description>Separate flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREGION</name>
<description>Number of MPU data regions</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IREGION</name>
<description>Number of MPU instruction regions</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_CTRL</name>
<displayName>MPU_CTRL</displayName>
<description>MPU control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the MPU</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFNMIENA</name>
<description>Enables the operation of MPU during hard fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIVDEFENA</name>
<description>Enable priviliged software access to default memory map</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_RNR</name>
<displayName>MPU_RNR</displayName>
<description>MPU region number register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_RBAR</name>
<displayName>MPU_RBAR</displayName>
<description>MPU region base address register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region field</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VALID</name>
<description>MPU region number valid</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Region base address field</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_RASR</name>
<displayName>MPU_RASR</displayName>
<description>MPU region attribute and size register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Region enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZE</name>
<description>Size of the MPU protection region</description>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SRD</name>
<description>Subregion disable bits</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>B</name>
<description>memory attribute</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>memory attribute</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S</name>
<description>Shareable memory attribute</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEX</name>
<description>memory attribute</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AP</name>
<description>Access permission</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>XN</name>
<description>Instruction access disable bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU</name>
<description>Floting point unit</description>
<groupName>FPU</groupName>
<baseAddress>0xE000EF34</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FPU</name>
<description>Floating point unit interrupt</description>
<value>54</value>
</interrupt>
<registers>
<register>
<name>FPCCR</name>
<displayName>FPCCR</displayName>
<description>Floating-point context control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSPACT</name>
<description>LSPACT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USER</name>
<description>USER</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THREAD</name>
<description>THREAD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFRDY</name>
<description>HFRDY</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRDY</name>
<description>MMRDY</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFRDY</name>
<description>BFRDY</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONRDY</name>
<description>MONRDY</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPEN</name>
<description>LSPEN</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASPEN</name>
<description>ASPEN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPCAR</name>
<displayName>FPCAR</displayName>
<description>Floating-point context address register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Location of unpopulated floating-point</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPSCR</name>
<displayName>FPSCR</displayName>
<description>Floating-point status control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOC</name>
<description>Invalid operation cumulative exception bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DZC</name>
<description>Division by zero cumulative exception bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFC</name>
<description>Overflow cumulative exception bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UFC</name>
<description>Underflow cumulative exception bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IXC</name>
<description>Inexact cumulative exception bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDC</name>
<description>Input denormal cumulative exception bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMode</name>
<description>Rounding Mode control field</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FZ</name>
<description>Flush-to-zero mode control bit:</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DN</name>
<description>Default NaN mode control bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHP</name>
<description>Alternative half-precision control bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>V</name>
<description>Overflow condition code flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>Carry condition code flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Z</name>
<description>Zero condition code flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>N</name>
<description>Negative condition code flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt Controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000E100</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x351</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISER0</name>
<displayName>ISER0</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER1</name>
<displayName>ISER1</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER0</name>
<displayName>ICER0</displayName>
<description>Interrupt Clear-Enable Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER1</name>
<displayName>ICER1</displayName>
<description>Interrupt Clear-Enable Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR0</name>
<displayName>ISPR0</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR1</name>
<displayName>ISPR1</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR0</name>
<displayName>ICPR0</displayName>
<description>Interrupt Clear-Pending Register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR1</name>
<displayName>ICPR1</displayName>
<description>Interrupt Clear-Pending Register</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR0</name>
<displayName>IABR0</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR1</name>
<displayName>IABR1</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR0</name>
<displayName>IPR0</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR1</name>
<displayName>IPR1</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR2</name>
<displayName>IPR2</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR3</name>
<displayName>IPR3</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x30C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR4</name>
<displayName>IPR4</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR5</name>
<displayName>IPR5</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x314</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR6</name>
<displayName>IPR6</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x318</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR7</name>
<displayName>IPR7</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x31C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR8</name>
<displayName>IPR8</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR9</name>
<displayName>IPR9</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x324</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR10</name>
<displayName>IPR10</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR11</name>
<displayName>IPR11</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x32C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR12</name>
<displayName>IPR12</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR13</name>
<displayName>IPR13</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x334</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR14</name>
<displayName>IPR14</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x338</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR15</name>
<displayName>IPR15</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x33C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR16</name>
<displayName>IPR16</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x340</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR17</name>
<displayName>IPR17</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x344</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC_STIR</name>
<description>Nested vectored interrupt controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000EF00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>STIR</name>
<displayName>STIR</displayName>
<description>Software trigger interrupt register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTID</name>
<description>Software generated interrupt ID</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB_ACTRL</name>
<description>System control block ACTLR</description>
<groupName>SCB</groupName>
<baseAddress>0xE000E008</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ACTRL</name>
<displayName>ACTRL</displayName>
<description>Auxiliary control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DISMCYCINT</name>
<description>DISMCYCINT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISDEFWBUF</name>
<description>DISDEFWBUF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFOLD</name>
<description>DISFOLD</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFPCA</name>
<description>DISFPCA</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISOOFP</name>
<description>DISOOFP</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU_CPACR</name>
<description>Floating point unit CPACR</description>
<groupName>FPU</groupName>
<baseAddress>0xE000ED88</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPACR</name>
<displayName>CPACR</displayName>
<description>Coprocessor access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000000</resetValue>
<fields>
<field>
<name>CP</name>
<description>CP</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>