389ff92cc1
* Makefile, Scripts: new linter * About: remove ID from IC * Firmware: remove double define for DIVC/DIVR * Scripts: check folder names too. Docker: replace syntax check with make lint. * Reformat Sources and Migrate to new file naming convention * Docker: symlink clang-format-12 to clang-format * Add coding style guide
212 lines
9.3 KiB
C
212 lines
9.3 KiB
C
#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Frequency Synthesizer constants */
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#define CC1101_QUARTZ 26000000
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#define CC1101_FMASK 0xFFFFFF
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#define CC1101_FDIV 0x10000
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#define CC1101_IFDIV 0x400
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/* IO Bus constants */
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#define CC1101_TIMEOUT 500
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/* Bits and pieces */
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#define CC1101_READ (1 << 7) /** Read Bit */
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#define CC1101_BURST (1 << 6) /** Burst Bit */
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/* Common registers, CC1101_BURST and CC1101_WRITE behaves as expected */
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#define CC1101_IOCFG2 0x00 /** GDO2 output pin configuration */
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#define CC1101_IOCFG1 0x01 /** GDO1 output pin configuration */
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#define CC1101_IOCFG0 0x02 /** GDO0 output pin configuration */
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#define CC1101_FIFOTHR 0x03 /** RX FIFO and TX FIFO thresholds */
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#define CC1101_SYNC1 0x04 /** Sync word, high byte */
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#define CC1101_SYNC0 0x05 /** Sync word, low byte */
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#define CC1101_PKTLEN 0x06 /** Packet length */
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#define CC1101_PKTCTRL1 0x07 /** Packet automation control */
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#define CC1101_PKTCTRL0 0x08 /** Packet automation control */
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#define CC1101_ADDR 0x09 /** Device address */
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#define CC1101_CHANNR 0x0A /** Channel number */
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#define CC1101_FSCTRL1 0x0B /** Frequency synthesizer control */
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#define CC1101_FSCTRL0 0x0C /** Frequency synthesizer control */
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#define CC1101_FREQ2 0x0D /** Frequency control word, high byte */
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#define CC1101_FREQ1 0x0E /** Frequency control word, middle byte */
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#define CC1101_FREQ0 0x0F /** Frequency control word, low byte */
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#define CC1101_MDMCFG4 0x10 /** Modem configuration */
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#define CC1101_MDMCFG3 0x11 /** Modem configuration */
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#define CC1101_MDMCFG2 0x12 /** Modem configuration */
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#define CC1101_MDMCFG1 0x13 /** Modem configuration */
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#define CC1101_MDMCFG0 0x14 /** Modem configuration */
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#define CC1101_DEVIATN 0x15 /** Modem deviation setting */
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#define CC1101_MCSM2 0x16 /** Main Radio Control State Machine configuration */
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#define CC1101_MCSM1 0x17 /** Main Radio Control State Machine configuration */
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#define CC1101_MCSM0 0x18 /** Main Radio Control State Machine configuration */
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#define CC1101_FOCCFG 0x19 /** Frequency Offset Compensation configuration */
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#define CC1101_BSCFG 0x1A /** Bit Synchronization configuration */
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#define CC1101_AGCCTRL2 0x1B /** AGC control */
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#define CC1101_AGCCTRL1 0x1C /** AGC control */
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#define CC1101_AGCCTRL0 0x1D /** AGC control */
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#define CC1101_WOREVT1 0x1E /** High byte Event 0 timeout */
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#define CC1101_WOREVT0 0x1F /** Low byte Event 0 timeout */
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#define CC1101_WORCTRL 0x20 /** Wake On Radio control */
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#define CC1101_FREND1 0x21 /** Front end RX configuration */
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#define CC1101_FREND0 0x22 /** Front end TX configuration */
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#define CC1101_FSCAL3 0x23 /** Frequency synthesizer calibration */
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#define CC1101_FSCAL2 0x24 /** Frequency synthesizer calibration */
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#define CC1101_FSCAL1 0x25 /** Frequency synthesizer calibration */
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#define CC1101_FSCAL0 0x26 /** Frequency synthesizer calibration */
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#define CC1101_RCCTRL1 0x27 /** RC oscillator configuration */
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#define CC1101_RCCTRL0 0x28 /** RC oscillator configuration */
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#define CC1101_FSTEST 0x29 /** Frequency synthesizer calibration control */
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#define CC1101_PTEST 0x2A /** Production test */
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#define CC1101_AGCTEST 0x2B /** AGC test */
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#define CC1101_TEST2 0x2C /** Various test settings */
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#define CC1101_TEST1 0x2D /** Various test settings */
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#define CC1101_TEST0 0x2E /** Various test settings */
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/* Strobe registers, CC1101_BURST is not available, CC1101_WRITE ignored */
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#define CC1101_STROBE_SRES 0x30 /** Reset chip. */
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#define CC1101_STROBE_SFSTXON \
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0x31 /** Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). */
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#define CC1101_STROBE_SXOFF 0x32 /** Turn off crystal oscillator. */
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#define CC1101_STROBE_SCAL \
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0x33 /** Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0) */
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#define CC1101_STROBE_SRX \
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0x34 /** Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1. */
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#define CC1101_STROBE_STX \
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0x35 /** In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear. */
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#define CC1101_STROBE_SIDLE \
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0x36 /** Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable. */
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#define CC1101_STROBE_SWOR \
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0x38 /** Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if WORCTRL.RC_PD=0. */
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/* 0x37 is unused */
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#define CC1101_STROBE_SPWD 0x39 /** Enter power down mode when CSn goes high. */
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#define CC1101_STROBE_SFRX \
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0x3A /** Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states. */
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#define CC1101_STROBE_SFTX \
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0x3B /** Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states. */
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#define CC1101_STROBE_SWORRST 0x3C /** Reset real time clock to Event1 value. */
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#define CC1101_STROBE_SNOP \
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0x3D /** No operation. May be used to get access to the chip status byte.*/
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/* Status registers, must be accessed with CC1101_BURST, but one by one */
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#define CC1101_STATUS_PARTNUM 0x30 /** Chip ID Part Number */
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#define CC1101_STATUS_VERSION 0x31 /** Chip ID Version */
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#define CC1101_STATUS_FREQEST 0x32 /** Frequency Offset Estimate from Demodulator */
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#define CC1101_STATUS_LQI 0x33 /** Demodulator Estimate for Link Quality, 7bit-CRC, 6..0-LQI*/
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#define CC1101_STATUS_RSSI 0x34 /** Received Signal Strength Indication */
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#define CC1101_STATUS_MARCSTATE 0x35 /** Main Radio Control State Machine State */
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#define CC1101_STATUS_WORTIME1 0x36 /** High Byte of WOR Time */
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#define CC1101_STATUS_WORTIME0 0x37 /** Low Byte of WOR Time */
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#define CC1101_STATUS_PKTSTATUS 0x38 /** Current GDOx Status and Packet Status */
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#define CC1101_STATUS_VCO_VC_DAC 0x39 /** Current Setting from PLL Calibration Module */
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#define CC1101_STATUS_TXBYTES \
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0x3A /** Underflow and Number of Bytes, 7bit-Underflow, 6..0-Number of Bytes*/
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#define CC1101_STATUS_RXBYTES \
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0x3B /** Overflow and Number of Bytes, 7bit-Overflow*, 6..0-Number of Bytes*/
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#define CC1101_STATUS_RCCTRL1_STATUS 0x3C /** Last RC Oscillator Calibration Result */
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#define CC1101_STATUS_RCCTRL0_STATUS 0x3D /** Last RC Oscillator Calibration Result */
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/* Some special registers, use CC1101_BURST to read/write data */
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#define CC1101_PATABLE \
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0x3E /** PATABLE register number, an 8-byte table that defines the PA control settings */
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#define CC1101_FIFO \
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0x3F /** FIFO register nunmber, can be combined with CC1101_WRITE and/or CC1101_BURST */
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#define CC1101_IOCFG_INV (1 << 6) /** IOCFG inversion */
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typedef enum {
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CC1101IocfgRxFifoThreshold = 0x00,
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CC1101IocfgRxFifoThresholdOrPacket = 0x01,
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CC1101IocfgTxFifoThreshold = 0x02,
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CC1101IocfgTxFifoFull = 0x03,
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CC1101IocfgRxOverflow = 0x04,
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CC1101IocfgTxUnderflow = 0x05,
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CC1101IocfgSyncWord = 0x06,
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CC1101IocfgPacket = 0x07,
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CC1101IocfgPreamble = 0x08,
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CC1101IocfgClearChannel = 0x09,
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CC1101IocfgLockDetector = 0x0A,
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CC1101IocfgSerialClock = 0x0B,
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CC1101IocfgSerialSynchronousDataOutput = 0x0C,
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CC1101IocfgSerialDataOutput = 0x0D,
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CC1101IocfgCarrierSense = 0x0E,
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CC1101IocfgCrcOk = 0x0F,
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/* Reserved range: 0x10 - 0x15 */
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CC1101IocfgRxHardData1 = 0x16,
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CC1101IocfgRxHardData0 = 0x17,
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/* Reserved range: 0x18 - 0x1A */
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CC1101IocfgPaPd = 0x1B,
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CC1101IocfgLnaPd = 0x1C,
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CC1101IocfgRxSymbolTick = 0x1D,
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/* Reserved range: 0x1E - 0x23 */
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CC1101IocfgWorEvnt0 = 0x24,
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CC1101IocfgWorEvnt1 = 0x25,
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CC1101IocfgClk256 = 0x26,
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CC1101IocfgClk32k = 0x27,
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/* Reserved: 0x28 */
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CC1101IocfgChpRdyN = 0x29,
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/* Reserved: 0x2A */
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CC1101IocfgXoscStable = 0x2B,
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/* Reserved range: 0x2C - 0x2D */
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CC1101IocfgHighImpedance = 0x2E,
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CC1101IocfgHW = 0x2F,
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/* Only one CC1101IocfgClkXoscN can be selected as an output at any time */
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CC1101IocfgClkXosc1 = 0x30,
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CC1101IocfgClkXosc1_5 = 0x31,
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CC1101IocfgClkXosc2 = 0x32,
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CC1101IocfgClkXosc3 = 0x33,
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CC1101IocfgClkXosc4 = 0x34,
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CC1101IocfgClkXosc6 = 0x35,
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CC1101IocfgClkXosc8 = 0x36,
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CC1101IocfgClkXosc12 = 0x37,
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CC1101IocfgClkXosc16 = 0x38,
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CC1101IocfgClkXosc24 = 0x39,
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CC1101IocfgClkXosc32 = 0x3A,
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CC1101IocfgClkXosc48 = 0x3B,
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CC1101IocfgClkXosc64 = 0x3C,
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CC1101IocfgClkXosc96 = 0x3D,
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CC1101IocfgClkXosc128 = 0x3E,
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CC1101IocfgClkXosc192 = 0x3F,
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} CC1101Iocfg;
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typedef enum {
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CC1101StateIDLE = 0b000, /** IDLE state */
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CC1101StateRX = 0b001, /** Receive mode */
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CC1101StateTX = 0b010, /** Transmit mode */
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CC1101StateFSTXON = 0b011, /** Fast TX ready */
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CC1101StateCALIBRATE = 0b100, /** Frequency synthesizer calibration is running */
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CC1101StateSETTLING = 0b101, /** PLL is settling */
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CC1101StateRXFIFO_OVERFLOW =
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0b110, /** RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX */
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CC1101StateTXFIFO_UNDERFLOW = 0b111, /** TX FIFO has underflowed. Acknowledge with SFTX */
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} CC1101State;
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typedef struct {
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uint8_t FIFO_BYTES_AVAILABLE : 4;
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CC1101State STATE : 3;
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bool CHIP_RDYn : 1;
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} CC1101Status;
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typedef union {
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CC1101Status status;
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uint8_t status_raw;
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} CC1101StatusRaw;
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typedef struct {
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uint8_t NUM_TXBYTES : 7;
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bool TXFIFO_UNDERFLOW : 1;
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} CC1101TxBytes;
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typedef struct {
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uint8_t NUM_RXBYTES : 7;
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bool RXFIFO_OVERFLOW : 1;
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} CC1101RxBytes;
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#ifdef __cplusplus
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}
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#endif |