あく 5439e232cc [FL-950] CC1101 Stage1, SPI Refactoring, Drivers layer (#386) ... * API HAL SPI: refactoring, split into layers, prepare ST HAL separation. API HAL SubGhz: initialize on start. Drivers: add basic cc1101 driver. Update API usage. Debug: increase max debugger port speed. Remove subghz apps. * CC1101: chip status handling. ApiHalSpi: increase SubGhz bus speed to 8mhz. F4: backport subghz initialization. * Api Hal SubGhz: rx path and frequency. CC1101: frequency control. * SubGhz Application: basic tests * SubGhz app: tone and packet test. API HAL SUBGHZ: update configs, add missing bits and pieces.		2021-03-31 20:52:26 +03:00
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api-hal	[FL-950] CC1101 Stage1, SPI Refactoring, Drivers layer (#386)	2021-03-31 20:52:26 +03:00
ble-glue	[FL-580] Prepare BLE for certification (#376)	2021-03-11 12:31:07 +03:00
Inc	[FL-950] CC1101 Stage1, SPI Refactoring, Drivers layer (#386)	2021-03-31 20:52:26 +03:00
Src	[FL-185] Gauge calibration (#391)	2021-03-26 14:23:31 +03:00
f4.ioc	[FL-667] Power saving: deep sleep in tickless state (#300)	2021-01-18 18:08:58 +03:00
startup_stm32wb55xx_cm4.s
stm32wb55xx_flash_cm4_boot.ld	Update linker script to match upper bound (#345)	2021-02-16 13:57:35 +03:00
stm32wb55xx_flash_cm4_no_boot.ld	Update linker script to match upper bound (#345)	2021-02-16 13:57:35 +03:00
stm32wb55xx_flash_cm4.ld	Update linker script to match upper bound (#345)	2021-02-16 13:57:35 +03:00
target.mk	API HAL OS: replace CMP based ticks with ARR based one, hard reset lptimer on reconfiguration. (#377)	2021-03-11 09:47:07 +03:00