f25d000d53
* ApiHal: console abstraction, change uart baud rate to 230400. Bootloader: drop F5. Furi: prevent thread local output to serial console in stdglue. * ApiHal: take control over system initialization, reorder some subsystems in a hope of fixing USB issues. * Main: cleanup dead code. ISR: take care of HSECSS by our self. USB: leave clock configuration alone. * F6 cube: switch RCC to LL. * Cli: rollback return behavior.
135 lines
4.2 KiB
C
135 lines
4.2 KiB
C
#include <api-hal-clock.h>
|
|
|
|
#include <main.h>
|
|
#include <stm32wbxx_ll_pwr.h>
|
|
#include <stm32wbxx_ll_rcc.h>
|
|
#include <stm32wbxx_ll_utils.h>
|
|
|
|
void api_hal_clock_init() {
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
|
|
while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3);
|
|
|
|
/* HSE configuration and activation */
|
|
LL_RCC_HSE_SetCapacitorTuning(0x18);
|
|
LL_RCC_HSE_Enable();
|
|
while(LL_RCC_HSE_IsReady() != 1) ;
|
|
|
|
/* HSI configuration and activation */
|
|
LL_RCC_HSI_Enable();
|
|
while(LL_RCC_HSI_IsReady() != 1)
|
|
|
|
/* LSE configuration and activation */
|
|
LL_PWR_EnableBkUpAccess();
|
|
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW);
|
|
LL_RCC_LSE_Enable();
|
|
while(LL_RCC_LSE_IsReady() != 1) ;
|
|
|
|
LL_RCC_HSE_EnableCSS();
|
|
LL_RCC_EnableIT_LSECSS();
|
|
LL_RCC_LSE_EnableCSS();
|
|
|
|
/* Main PLL configuration and activation */
|
|
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 8, LL_RCC_PLLR_DIV_2);
|
|
LL_RCC_PLL_Enable();
|
|
LL_RCC_PLL_EnableDomain_SYS();
|
|
while(LL_RCC_PLL_IsReady() != 1);
|
|
|
|
LL_RCC_PLLSAI1_ConfigDomain_48M(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1Q_DIV_2);
|
|
LL_RCC_PLLSAI1_ConfigDomain_ADC(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1R_DIV_2);
|
|
LL_RCC_PLLSAI1_Enable();
|
|
LL_RCC_PLLSAI1_EnableDomain_48M();
|
|
LL_RCC_PLLSAI1_EnableDomain_ADC();
|
|
while(LL_RCC_PLLSAI1_IsReady() != 1);
|
|
|
|
/* Sysclk activation on the main PLL */
|
|
/* Set CPU1 prescaler*/
|
|
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
|
|
|
/* Set CPU2 prescaler*/
|
|
LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
|
|
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
|
|
|
|
/* Set AHB SHARED prescaler*/
|
|
LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
|
|
|
|
/* Set APB1 prescaler*/
|
|
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
|
|
|
/* Set APB2 prescaler*/
|
|
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
|
|
|
/* Disable MSI */
|
|
LL_RCC_MSI_Disable();
|
|
while(LL_RCC_MSI_IsReady() != 0);
|
|
|
|
/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
|
|
LL_SetSystemCoreClock(64000000);
|
|
|
|
/* Update the time base */
|
|
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
|
|
{
|
|
Error_Handler();
|
|
}
|
|
|
|
if(LL_RCC_GetRTCClockSource() != LL_RCC_RTC_CLKSOURCE_LSE) {
|
|
LL_RCC_ForceBackupDomainReset();
|
|
LL_RCC_ReleaseBackupDomainReset();
|
|
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
|
|
}
|
|
|
|
LL_RCC_EnableRTC();
|
|
|
|
LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2);
|
|
LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_PLLSAI1);
|
|
LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
|
|
LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_CLK48);
|
|
LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLLSAI1);
|
|
LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
|
|
LL_RCC_SetSMPSPrescaler(LL_RCC_SMPS_DIV_1);
|
|
LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
|
|
|
|
// AHB1
|
|
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
|
|
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
|
|
|
|
// AHB2
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
|
|
|
|
// APB1
|
|
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
|
|
|
|
// APB2
|
|
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
|
|
}
|
|
|
|
void api_hal_clock_switch_to_hsi() {
|
|
LL_RCC_HSI_Enable( );
|
|
|
|
while(!LL_RCC_HSI_IsReady());
|
|
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
|
|
LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
|
|
|
|
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
|
|
}
|
|
|
|
void api_hal_clock_switch_to_pll() {
|
|
LL_RCC_HSE_Enable();
|
|
LL_RCC_PLL_Enable();
|
|
|
|
while(!LL_RCC_HSE_IsReady());
|
|
while(!LL_RCC_PLL_IsReady());
|
|
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
|
LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
|
|
|
|
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
|
|
}
|