851a44dc59
* Gui: input injection in screen stream * Cli: expose ASCII table in public header * SubGhz: dma output draft * SubGhz: output initialization cleanup * SubGhz: update dma send routine, add subghz_tx cli command. * SubGhz: proper register address for DMA * SubGhz: proper, fully working dma+tim2 configuration * SubGhz: transmit PT with cli. * Drivers: fix invalid size in CC1101 PA_TABLE loading routine. * Interrupts: configurable DMA isrs. * F5: backport fixes. * SubGhz: free buffer after use * SubGhz: use sleep instead of reset at the end * SubGhz: async tx repeat with circular DMA * SubGhz: disable dma channel on complete, adjust PT send timings * SubGhz: backport function singature change to F5 * SubGhz: add tx debug gpio
37 lines
917 B
C
37 lines
917 B
C
#include <api-hal-clock.h>
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#include <stm32wbxx_ll_rcc.h>
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void api_hal_clock_init() {
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// AHB
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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// APB
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
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}
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void api_hal_clock_switch_to_hsi() {
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LL_RCC_HSI_Enable( );
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while(!LL_RCC_HSI_IsReady());
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
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}
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void api_hal_clock_switch_to_pll() {
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LL_RCC_HSE_Enable();
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LL_RCC_PLL_Enable();
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while(!LL_RCC_HSE_IsReady());
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while(!LL_RCC_PLL_IsReady());
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
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}
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