147 lines
3.0 KiB
Markdown
147 lines
3.0 KiB
Markdown
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Code from 4 person hacking session on 11/11.
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The following code may or may not work properly - It appears to give relatively sane counter output in GTKWAVE.
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// FALLING EDGE D FLIP FLIP MODULE:
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//==============================================
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module d_ff_gates (d, clk, rst, q, q_bar);
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input d, clk, rst;
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output q, q_bar;
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wire n1,n2,n3,q_bar_n;
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wire cn,dn,n4,n5,n6;
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// First Latch
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not (n1,d);
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nand (n2,d,clk);
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nand (n3,n1,clk);
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nand (dn,q_bar_n,n2);
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nand (q_bar_n,dn,n3, !rst);
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// Second Latch
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not (cn,clk);
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not (n4,dn);
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nand (n5,dn,cn);
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nand (n6,n4,cn);
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nand (q,q_bar,n5);
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nand (q_bar,q,n6, !rst);
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endmodule
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// FALLING EDGE D FLIP FLIP TESTBENCH:
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//==============================================
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module d_ff_gates_tb;
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reg d, clk;
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wire q, q_bar;
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d_ff_gates dut(d, clk, q, q_bar);
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initial
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begin
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d=0; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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d=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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end
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initial
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begin
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$dumpfile ("waves.lxt");
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$dumpvars (0, d_ff_gates_tb);
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end
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endmodule
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// 4 BIT COUNTER MODULE:
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//==============================================
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module upcounter (rst, clk, enable, q, qb);
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input rst, clk, enable;
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output [3:0] q, qb;
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wire d0, d1, d2, d3; // input wires
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wire a0, a1; // and wires
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//q[1] = 1'b0; q[2] = 1'b0; q[3] = 1'b0; // init q
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xor (d0, q[0], 1'b1); // d0 = q0 xor 1
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d_ff_gates dff0(d0, clk, rst, q[0], qb[0]);
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xor (d1, q[1], q[0]); // d1 = q1 xor q0
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d_ff_gates dff1(d1, clk, rst, q[1], qb[1]);
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and (a0, q[1], q[0]);
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xor (d2, q[2], a0); // d2 = q2 xor (q1 && q0)
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d_ff_gates dff2(d2, clk, rst, q[2], qb[2]);
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and (a1, q[2], q[1]);
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xor (d3, q[3], a1); // d3 = q3 xor (q2 && q1 && q0)
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d_ff_gates dff3(d3, clk, rst, q[3], qb[3]);
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endmodule
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// 4 BIT COUNTER TESTBENCH:
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//==============================================
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module upcounter_tb;
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reg rst, clk, enable;
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wire [3:0] q, qb;
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upcounter dut(rst, clk, enable, q, qb);
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initial
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begin
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rst = 1;
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enable = 0;
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clk=0; #1;
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rst = 0;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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clk=0; #1;
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clk=1; #1;
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end
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initial
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begin
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$dumpfile ("waves.lxt");
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$dumpvars (0, upcounter_tb);
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end
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endmodule
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[Category:FPGAWorkshop](Category:FPGAWorkshop "wikilink")
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