255 lines
5.4 KiB
Markdown
255 lines
5.4 KiB
Markdown
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## Shift Register
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//filename sr.v
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`include "timescale.v"
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module sr(D, Q, Q_regs, clk, rst);
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parameter Ndepth=4;
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parameter TP=1;
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input D, clk, rst;
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output Q;
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output [Ndepth-1:0] Q_regs;
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reg [Ndepth-1:0] Q_regs;
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assign Q = Q_regs[Ndepth-1];
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/* This is a comment block
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Hi Elliot
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This works fine! */
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always@(posedge clk)
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if(rst)
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Q_regs <= #TP 0; //This is a comment
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else
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Q_regs <= #TP {Q_regs[Ndepth-2:0],D};
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endmodule
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## Shift Register Testbench
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//
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// filename sr_tb.v
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//
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// Exercise 6
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// FPGA Workshop - HacDC
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// Group think
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//
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`include "timescale.v"
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module sr_tb();
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// Parameters
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parameter CLKPERIOD = 20; // 50Mhz w/ 1ns time increments
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parameter FINISHTIME = 1000;
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// DUT INPUTS
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reg D;
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reg clk;
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reg rst;
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// DUT OUTPUTS
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wire Q;
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wire [3:0] Q_regs;
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// Misc
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reg finish;
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// Event defitions
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event reset;
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// DUT Instantiation
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// shift(.D(), .Q(), .Q_regs(), .clk(), .rst());
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sr DUT(.D(D),
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.Q(Q),
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.Q_regs(Q_regs),
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.clk(clk),
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.rst(rst));
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// --------
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// Stimulus
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// --------
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// Clk Generation
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always
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#(CLKPERIOD/2) clk = ~clk;
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// Initial Conditions
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initial
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begin
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D = 0;
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rst = 0;
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clk = 1;
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finish = 0;
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// Wait to end the simulation
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#FINISHTIME
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$display("=============================");
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$display("I'm done now!");
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$display("Finished at time %5d", $time);
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$finish;
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end
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// Inputs
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initial
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begin
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#1 -> reset; //event calls like to occur after some
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//period of time
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wait(finish);
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finish = 0;
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repeat (5)
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#CLKPERIOD;
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D=1;
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wait (Q);
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#CLKPERIOD
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D=1;
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#CLKPERIOD
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D=0;
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#CLKPERIOD
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D=1;
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#CLKPERIOD
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D=0;
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repeat (5)
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#CLKPERIOD;
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$display("================");
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$display("End of Stimulus");
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$display("Finishing at time %5d", $time);
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$finish;
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end
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// Event defitions
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always @(reset)
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begin
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$display ("Resetting the Registers");
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#(CLKPERIOD/2) rst = 1;
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#CLKPERIOD rst = 0;
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finish = 1;
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end
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// Monitor
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initial
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begin
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$dumpfile ("waves.lxt");
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$dumpvars(0,sr_tb);
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end
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endmodule
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## Linear Feedback Shift Register
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module lfsr(Q, Q_regs, clk, rst);
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// x^5+x^3+1
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parameter N=5;
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parameter Tp=1;
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input clk, rst;
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output Q;
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output [N-1:0]
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Q_regs; reg [N-1:0] Q_regs;
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assign Q = Q_regs[0];
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always@(posedge clk)
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if(rst)
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Q_regs<= #Tp 5'b1;
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else
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Q_regs<= #Tp {Q_regs[3], Q_regs[2], Q_regs[1], Q_regs[0], Q_regs[4]^Q_regs[2]};
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endmodule
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## LFSR Testbench
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//
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// Exercise 6
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// FPGA Workshop - HacDC
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// Group think
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//
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`include "timescale.v"
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module lfsr_tb();
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// Parameters
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parameter CLKPERIOD = 20; // 50Mhz w/ 1ns time increments
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parameter FINISHTIME = 2*1000;
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// DUT INPUTS
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reg clk;
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reg rst;
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// DUT OUTPUTS
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wire Q;
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wire [4:0] Q_regs;
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// Misc
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reg finish;
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// Event defitions
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event reset;
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// DUT Instantiation
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// lfsr(.Q(), .Q_regs(), .clk(), .rst());
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lfsr DUT(.Q(Q),
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.Q_regs(Q_regs),
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.clk(clk),
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.rst(rst));
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// --------
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// Stimulus
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// --------
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// Clk Generation
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always
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#(CLKPERIOD/2) clk = ~clk;
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// Initial Conditions
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initial
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begin
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rst = 0;
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clk = 1;
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finish = 0;
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// Wait to end the simulation
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#FINISHTIME
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$display("=============================");
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$display("I'm done now!");
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$display("Finished at time %5d", $time);
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$finish;
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end
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// Inputs
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initial
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begin
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#1 -> reset; //event calls like to occur after some
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//period of time
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wait(finish);
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finish = 0;
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repeat (62)
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#CLKPERIOD;
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$display("================");
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$display("End of Stimulus");
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$display("Finishing at time %5d", $time);
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$finish;
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end
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// Event defitions
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always @(reset)
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begin
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$display ("Resetting the Registers");
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#(CLKPERIOD/2) rst = 1;
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#CLKPERIOD rst = 0;
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finish = 1;
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end
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// Monitor
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initial
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begin
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$dumpfile ("waves.lxt");
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$dumpvars(0,lfsr_tb);
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end
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endmodule
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## Timescale
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//
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// filename timescale.v
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//
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`timescale 1ns / 10ps
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[Category:FPGAWorkshop](Category:FPGAWorkshop "wikilink")
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