alignment refactor

veilid-core/src/veilid_api/aligned_u64.rs

@@ -89,6 +89,12 @@ impl<Rhs: Into<u64>> core::ops::Mul<Rhs> for AlignedU64 {
     }
 }
 
+impl<Rhs: Into<u64>> core::ops::MulAssign<Rhs> for AlignedU64 {
+    fn mul_assign(&mut self, rhs: Rhs) {
+        self.0 *= rhs.into();
+    }
+}
+
 impl<Rhs: Into<u64>> core::ops::Div<Rhs> for AlignedU64 {
     type Output = Self;
 
@@ -97,6 +103,12 @@ impl<Rhs: Into<u64>> core::ops::Div<Rhs> for AlignedU64 {
     }
 }
 
+impl<Rhs: Into<u64>> core::ops::DivAssign<Rhs> for AlignedU64 {
+    fn div_assign(&mut self, rhs: Rhs) {
+        self.0 /= rhs.into();
+    }
+}
+
 impl AlignedU64 {
     pub const fn new(v: u64) -> Self {
         Self(v)

veilid-core/src/veilid_api/types.rs

@@ -1961,7 +1961,7 @@ impl SignedRelayedNodeInfo {
         sig_bytes.append(&mut builder_to_vec(ri_msg).map_err(VeilidAPIError::internal)?);
 
         // Add timestamp to signature
-        sig_bytes.append(&mut timestamp.to_le_bytes().to_vec());
+        sig_bytes.append(&mut timestamp.as_u64().to_le_bytes().to_vec());
 
         Ok(sig_bytes)
     }