FL-524 Fix subghz freq (#303)
* add freq tuning * remove force VCO from test settinigs
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coreglitch
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6a5e3e83b4
@ -32,15 +32,15 @@ typedef struct {
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uint16_t channel;
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} FreqConfig;
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void setup_freq(CC1101* cc1101, const FreqConfig* config) {
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void setup_freq(CC1101* cc1101, float freq) {
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// cc1101->SpiWriteReg(CC1101_MCSM0, 0x08); // disalbe FS_AUTOCAL
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// cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43 | 0x0C); // MAX_DVGA_GAIN to 11 for fast rssi
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// cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0xB0); // max AGC WAIT_TIME; 0 filter_length
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// cc1101->SetMod(GFSK); // set to GFSK for fast rssi measurement | +8 is dcfilter off
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uint32_t freq_reg = config->band->base_freq * 1e6 / (F_OSC / 65536);
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uint32_t freq_reg = freq * 1e6 / (F_OSC / 65536);
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cc1101->SetFreq((freq_reg >> 16) & 0xFF, (freq_reg >> 8) & 0xFF, (freq_reg)&0xFF);
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cc1101->SetChannel(config->channel);
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cc1101->SetChannel(0);
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/*
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//set test0 to 0x09
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@ -117,22 +117,12 @@ int16_t rx_rssi(CC1101* cc1101, const FreqConfig* config) {
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return rssi_dBm;
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}
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/*
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void flp_config(CC1101* cc1101) {
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// cc1101->SpiWriteReg(CC1101_FSCTRL1, 0x06); //IF frequency
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// cc1101->SpiWriteReg(CC1101_FSCTRL0, 0x00); //frequency offset before synthesizer
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// cc1101->SpiWriteReg(CC1101_MDMCFG4, 0xCC); // RX filter bandwidth 100k(0xcc)
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// cc1101->SpiWriteReg(CC1101_MDMCFG3, 0x43); //datarate config 512kBaud for the purpose of fast rssi measurement
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// cc1101->SpiWriteReg(CC1101_MDMCFG1, 0x21); //FEC preamble etc. last 2 bits for channel spacing
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// cc1101->SpiWriteReg(CC1101_MDMCFG0, 0xF8); //100khz channel spacing
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// CC1101_CHANNR moved to SetChannel func
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cc1101->SpiWriteReg(
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CC1101_MCSM0, 0x18); // calibrate when going from IDLE to RX or TX ; 149 - 155 μs timeout
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// MCSM0.FS_AUTOCAL[1:0] = 1
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// cc1101->SpiSetRegValue(CC1101_MCSM0, 1, 5, 4); // this not work
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// cc1101->SpiWriteReg(CC1101_FOCCFG, 0x16); //frequency compensation
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cc1101->SpiWriteReg(CC1101_AGCCTRL2, 0x43);
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cc1101->SpiWriteReg(CC1101_AGCCTRL1, 0x49);
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cc1101->SpiWriteReg(CC1101_AGCCTRL0, 0x91);
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@ -142,19 +132,10 @@ void flp_config(CC1101* cc1101) {
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cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A);
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cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00);
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cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F);
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// cc1101->SpiWriteReg(CC1101_TEST2, 0x81);
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// cc1101->SpiWriteReg(CC1101_TEST1, 0x35);
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// cc1101->SpiWriteReg(CC1101_TEST0, 0x0B); //should be 0x0B for lower than 430.6MHz and 0x09 for higher
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// cc1101->SpiWriteReg(CC1101_IOCFG2, 0x0D); //data output pin for asynchronous mode
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// cc1101->SpiWriteReg(CC1101_IOCFG0, 0x2E); //High impedance (3-state), GDO0 configed as data input for asynchronous mode
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// cc1101->SpiWriteReg(CC1101_PKTCTRL0, 0x33); //whitening off; asynchronous serial mode; CRC diable；reserved
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// cc1101->SpiWriteReg(CC1101_FIFOTHR, 0x47); //Adc_retention enabled for RX filter bandwidth less than 325KHz; defalut fifo threthold.
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// === Transparent mode ===
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// async data out
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cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0);
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cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
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cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // WAT
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// FIFOTHR.ADC_RETENTION = 1
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cc1101->SpiSetRegValue(CC1101_FIFOTHR, 1, 6, 6);
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@ -184,68 +165,13 @@ void flp_config(CC1101* cc1101) {
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printf("wrong bitrate\n");
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}
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cc1101->SetReceive();
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// mod
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// MDMCFG2.MOD_FORMAT = 3 (3: OOK, 0: 2-FSK)
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cc1101->SpiSetRegValue(CC1101_MDMCFG2, 3, 6, 4);
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// MDMCFG2.SYNC_MODE = 0
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cc1101->SpiSetRegValue(CC1101_MDMCFG2, 0, 2, 0);
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}
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void async_config(CC1101* cc1101) {
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cc1101->SpiSetRegValue(CC1101_IOCFG0, 13, 5, 0); // GDO0 Output Pin Configuration
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// FIFOTHR.ADC_RETENTION = 1
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cc1101->SpiSetRegValue(CC1101_FIFOTHR, 1, 6, 6);
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// PKTCTRL1.APPEND_STATUS = 0
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cc1101->SpiSetRegValue(CC1101_PKTCTRL1, 0, 2, 2);
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cc1101->SpiWriteReg(CC1101_PKTCTRL0, 0x32); // Packet Automation Control
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/*
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FIXME: this sequence not work
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// PKTCTRL0.PKT_FORMAT = 3
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cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 3, 5, 4);
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// PKTCTRL0.LENGTH_CONFIG = 2 // Infinite packet length mode
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cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 2, 1, 0);
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// PKTCTRL0.CRC_EN = 0
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cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 2, 2);
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// PKTCTRL0.WHITE_DATA = 0
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cc1101->SpiSetRegValue(CC1101_PKTCTRL0, 0, 6, 6);
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*/
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cc1101->SpiWriteReg(CC1101_MDMCFG4, 0xD6); //Modem Configuration
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cc1101->SpiWriteReg(CC1101_MDMCFG3, 0xE4); //Modem Configuration
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/*
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FIXME: not work
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// bandwidth 50-100 kHz
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if(!cc1101->setRxBandwidth(75.0)) {
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printf("wrong rx bw\n");
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}
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// datarate ~30 kbps
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if(!cc1101->setBitRate(100.)) {
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printf("wrong bitrate\n");
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}
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*/
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cc1101->SpiWriteReg(CC1101_MDMCFG2, 0x30); //Modem Configuration
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/*
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FIXME: not work
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// MDMCFG2.MOD_FORMAT = 3 (3: OOK, 0: 2-FSK)
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cc1101->SpiSetRegValue(CC1101_MDMCFG2, 3, 6, 4);
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// MDMCFG2.SYNC_MODE = 0
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cc1101->SpiSetRegValue(CC1101_MDMCFG2, 0, 2, 0);
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*/
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cc1101->SpiWriteReg(CC1101_MCSM0, 0x18); //Main Radio Control State Machine Configuration
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cc1101->SpiWriteReg(CC1101_FSCAL3, 0xE9); //Frequency Synthesizer Calibration
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cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A); //Frequency Synthesizer Calibration
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cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00); //Frequency Synthesizer Calibration
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cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F); //Frequency Synthesizer Calibration
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}
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*/
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void tx_config(CC1101* cc1101) {
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// cc1101->SpiWriteReg(CC1101_IOCFG2,0x0B); //GDO2 Output Pin Configuration
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@ -270,9 +196,12 @@ void tx_config(CC1101* cc1101) {
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cc1101->SpiWriteReg(CC1101_FSCAL2, 0x2A); //Frequency Synthesizer Calibration
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cc1101->SpiWriteReg(CC1101_FSCAL1, 0x00); //Frequency Synthesizer Calibration
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cc1101->SpiWriteReg(CC1101_FSCAL0, 0x1F); //Frequency Synthesizer Calibration
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/*
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cc1101->SpiWriteReg(CC1101_TEST2, 0x81); //Various Test Settings
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cc1101->SpiWriteReg(CC1101_TEST1, 0x35); //Various Test Settings
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cc1101->SpiWriteReg(CC1101_TEST0, 0x09); //Various Test Settings
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*/
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}
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// f = (f_osc/65536) * (FREQ + CHAN * (256 + CH_SP_M) * 2^(CH_SP_E - 2))
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@ -285,7 +214,7 @@ const Band bands[] = {
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{300., {0x00, 0x00, 0x00}, 0, 255, 74},
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{315., {0x00, 0x00, 0x00}, 0, 255, 74},
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{348., {0x00, 0x00, 0x00}, 0, 255, 74},
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{387., {0x00, 0x00, 0x00}, 0, 255, 74},
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{386., {0x00, 0x00, 0x00}, 0, 255, 74},
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{433.92, {0x00, 0x00, 0x00}, 0, 255, 74},
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{438.9, {0x00, 0x00, 0x00}, 0, 255, 74},
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{464., {0x00, 0x00, 0x00}, 0, 255, 74},
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@ -341,7 +270,8 @@ const TxLevel TX_LEVELS[] = {
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typedef struct {
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Mode mode;
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size_t active_freq;
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size_t active_freq_idx;
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float active_freq;
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int16_t last_rssi;
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size_t tx_level;
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bool need_cc1101_conf;
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@ -359,9 +289,11 @@ static void render_callback(Canvas* canvas, void* ctx) {
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{
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char buf[24];
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FreqConfig conf = FREQ_LIST[state->active_freq];
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float freq = conf.band->base_freq + CHAN_SPA * conf.channel;
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sprintf(buf, "freq: %ld.%02ld MHz", (uint32_t)freq, (uint32_t)(freq * 100.) % 100);
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sprintf(
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buf,
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"freq: %ld.%02ld MHz",
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(uint32_t)state->active_freq,
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(uint32_t)(state->active_freq * 100.) % 100);
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canvas_set_font(canvas, FontSecondary);
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canvas_draw_str(canvas, 2, 25, buf);
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@ -417,7 +349,11 @@ extern "C" void cc1101_workaround(void* p) {
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State _state;
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_state.mode = ModeRx;
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_state.active_freq = 4;
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_state.active_freq_idx = 4;
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FreqConfig conf = FREQ_LIST[_state.active_freq_idx];
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_state.active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
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_state.need_cc1101_conf = true;
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_state.last_rssi = 0;
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_state.tx_level = 0;
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@ -465,7 +401,6 @@ extern "C" void cc1101_workaround(void* p) {
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cc1101.SpiStrobe(CC1101_SIDLE);
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// flp_config(&cc1101);
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// async_config(&cc1101);
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tx_config(&cc1101);
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// setup_freq(&cc1101, &FREQ_LIST[4]);
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// enable_cc1101_irq();
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@ -498,27 +433,49 @@ extern "C" void cc1101_workaround(void* p) {
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furiac_exit(NULL);
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}
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if(event.value.input.state && event.value.input.input == InputUp) {
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if(state->active_freq > 0) {
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state->active_freq--;
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state->need_cc1101_conf = true;
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}
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}
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if(event.value.input.state && event.value.input.input == InputDown) {
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if(state->active_freq < (sizeof(FREQ_LIST) / sizeof(FREQ_LIST[0]) - 1)) {
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state->active_freq++;
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state->need_cc1101_conf = true;
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if(state->active_freq_idx > 0) {
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state->active_freq_idx--;
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}
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FreqConfig conf = FREQ_LIST[state->active_freq_idx];
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state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
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state->need_cc1101_conf = true;
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}
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if(event.value.input.state && event.value.input.input == InputLeft) {
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if(event.value.input.state && event.value.input.input == InputUp) {
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if(state->active_freq_idx < (sizeof(FREQ_LIST) / sizeof(FREQ_LIST[0]) - 1)) {
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state->active_freq_idx++;
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}
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FreqConfig conf = FREQ_LIST[state->active_freq_idx];
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state->active_freq = conf.band->base_freq + CHAN_SPA * conf.channel;
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state->need_cc1101_conf = true;
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}
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if(event.value.input.state && event.value.input.input == InputRight) {
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/*
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if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
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state->tx_level++;
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} else {
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state->tx_level = 0;
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}
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*/
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state->active_freq += 0.25;
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state->need_cc1101_conf = true;
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}
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if(event.value.input.state && event.value.input.input == InputLeft) {
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/*
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if(state->tx_level < (sizeof(TX_LEVELS) / sizeof(TX_LEVELS[0]) - 1)) {
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state->tx_level++;
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} else {
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state->tx_level = 0;
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}
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*/
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state->active_freq -= 0.25;
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state->need_cc1101_conf = true;
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}
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@ -535,14 +492,14 @@ extern "C" void cc1101_workaround(void* p) {
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cc1101.SpiStrobe(CC1101_SIDLE);
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gpio_init(&cc1101_g0_gpio, GpioModeInput);
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setup_freq(&cc1101, &FREQ_LIST[state->active_freq]);
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setup_freq(&cc1101, state->active_freq);
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cc1101.SetReceive();
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state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq]);
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state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
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} else if(state->mode == ModeTx) {
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cc1101.SpiStrobe(CC1101_SIDLE);
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setup_freq(&cc1101, &FREQ_LIST[state->active_freq]);
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setup_freq(&cc1101, state->active_freq);
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cc1101.SetTransmit();
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gpio_init(&cc1101_g0_gpio, GpioModeOutputPushPull);
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gpio_write(&cc1101_g0_gpio, false);
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@ -552,7 +509,8 @@ extern "C" void cc1101_workaround(void* p) {
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}
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if(!state->need_cc1101_conf && state->mode == ModeRx) {
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state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq]);
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// TOOD what about rssi offset
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state->last_rssi = rx_rssi(&cc1101, &FREQ_LIST[state->active_freq_idx]);
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gpio_write(led_record, state->last_rssi < RSSI_THRESHOLD);
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} else if(!state->need_cc1101_conf && state->mode == ModeTx) {
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