Allow pins 0 and 1 as RTS/DTR for USB UART Bridge (#1864)

* Allow pins 0 and 1 as RTS/DTR for USB UART Bridge * add logic to gpio_scene_usb_uart_config, fix flow_pins * fixing count of pins * disable PC0,PC1 RTS/DTR when using LPUART * add logic to ensure flow pins dont overlap with uart lines Co-authored-by: あく <alleteam@gmail.com>
2022-10-18 08:06:18 -07:00
parent 56f760aa07
commit 72713d6f4e
5 changed files with 37 additions and 2 deletions
--- a/applications/main/gpio/usb_uart_bridge.c
+++ b/applications/main/gpio/usb_uart_bridge.c
@@ -14,6 +14,7 @@
 static const GpioPin* flow_pins[][2] = {
    {&gpio_ext_pa7, &gpio_ext_pa6}, // 2, 3
    {&gpio_ext_pb2, &gpio_ext_pc3}, // 6, 7
+    {&gpio_ext_pc0, &gpio_ext_pc1}, // 16, 15
 };

 typedef enum {