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[FL-635] Enable LSE CSS (#371)

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* LSE CSS: explicitly configure and start LSE + LSI1 and enable LSECSS at boot, enable LSECSS interrupt in firmware.
* F4: backport LSE CSS shenanigans.
* Split LSE/HSE CSS handling routines, add TODO for missing notification.
This commit is contained in:
あく 2021-03-08 18:55:51 +03:00 committed by GitHub
parent 73e5379520
commit 9df4d8e2ed
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GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 48 additions and 38 deletions
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12
bootloader/targets/f4/target.c
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@ -31,6 +31,8 @@
#define BOOT_USB_DP_PIN LL_GPIO_PIN_12 #define BOOT_USB_DP_PIN LL_GPIO_PIN_12
#define BOOT_USB_PIN (BOOT_USB_DM_PIN | BOOT_USB_DP_PIN) #define BOOT_USB_PIN (BOOT_USB_DM_PIN | BOOT_USB_DP_PIN)
#define RTC_CLOCK_IS_READY() (LL_RCC_LSE_IsReady() && LL_RCC_LSI1_IsReady())
void target_led_control(char* c) { void target_led_control(char* c) {
LL_GPIO_SetOutputPin(LED_RED_PORT, LED_RED_PIN); LL_GPIO_SetOutputPin(LED_RED_PORT, LED_RED_PIN);
LL_GPIO_SetOutputPin(LED_GREEN_PORT, LED_GREEN_PIN); LL_GPIO_SetOutputPin(LED_GREEN_PORT, LED_GREEN_PIN);
@ -98,17 +100,19 @@ void gpio_init() {
void rtc_init() { void rtc_init() {
// LSE and RTC // LSE and RTC
LL_PWR_EnableBkUpAccess(); LL_PWR_EnableBkUpAccess();
if(!LL_RCC_LSE_IsReady()) { if(!RTC_CLOCK_IS_READY()) {
// Start LSI1 needed for CSS
LL_RCC_LSI1_Enable();
// Try to start LSE normal way // Try to start LSE normal way
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW); LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW);
LL_RCC_LSE_Enable(); LL_RCC_LSE_Enable();
uint32_t c = 0; uint32_t c = 0;
while(!LL_RCC_LSE_IsReady() && c < 200) { while(!RTC_CLOCK_IS_READY() && c < 200) {
LL_mDelay(10); LL_mDelay(10);
c++; c++;
} }
// Plan B: reset backup domain // Plan B: reset backup domain
if(!LL_RCC_LSE_IsReady()) { if(!RTC_CLOCK_IS_READY()) {
target_led_control("-R.R.R."); target_led_control("-R.R.R.");
LL_RCC_ForceBackupDomainReset(); LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset(); LL_RCC_ReleaseBackupDomainReset();
@ -116,6 +120,8 @@ void rtc_init() {
} }
// Set RTC domain clock to LSE // Set RTC domain clock to LSE
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE); LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
// Enable LSE CSS
LL_RCC_LSE_EnableCSS();
} }
// Enable clocking // Enable clocking
LL_RCC_EnableRTC(); LL_RCC_EnableRTC();

12
bootloader/targets/f5/target.c
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@ -23,6 +23,8 @@
#define BOOT_USB_DP_PIN LL_GPIO_PIN_12 #define BOOT_USB_DP_PIN LL_GPIO_PIN_12
#define BOOT_USB_PIN (BOOT_USB_DM_PIN | BOOT_USB_DP_PIN) #define BOOT_USB_PIN (BOOT_USB_DM_PIN | BOOT_USB_DP_PIN)
#define RTC_CLOCK_IS_READY() (LL_RCC_LSE_IsReady() && LL_RCC_LSI1_IsReady())
void target_led_control(char* c) { void target_led_control(char* c) {
api_hal_light_set(LightRed, 0x00); api_hal_light_set(LightRed, 0x00);
api_hal_light_set(LightGreen, 0x00); api_hal_light_set(LightGreen, 0x00);
@ -80,17 +82,19 @@ void gpio_init() {
void rtc_init() { void rtc_init() {
// LSE and RTC // LSE and RTC
LL_PWR_EnableBkUpAccess(); LL_PWR_EnableBkUpAccess();
if(!LL_RCC_LSE_IsReady()) { if(!RTC_CLOCK_IS_READY()) {
// Start LSI1 needed for CSS
LL_RCC_LSI1_Enable();
// Try to start LSE normal way // Try to start LSE normal way
LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW); LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW);
LL_RCC_LSE_Enable(); LL_RCC_LSE_Enable();
uint32_t c = 0; uint32_t c = 0;
while(!LL_RCC_LSE_IsReady() && c < 200) { while(!RTC_CLOCK_IS_READY() && c < 200) {
LL_mDelay(10); LL_mDelay(10);
c++; c++;
} }
// Plan B: reset backup domain // Plan B: reset backup domain
if(!LL_RCC_LSE_IsReady()) { if(!RTC_CLOCK_IS_READY()) {
target_led_control("-R.R.R."); target_led_control("-R.R.R.");
LL_RCC_ForceBackupDomainReset(); LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset(); LL_RCC_ReleaseBackupDomainReset();
@ -98,6 +102,8 @@ void rtc_init() {
} }
// Set RTC domain clock to LSE // Set RTC domain clock to LSE
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE); LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
// Enable LSE CSS
LL_RCC_LSE_EnableCSS();
} }
// Enable clocking // Enable clocking
LL_RCC_EnableRTC(); LL_RCC_EnableRTC();

13
firmware/targets/f4/Src/main.c
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@ -72,11 +72,12 @@ void SystemClock_Config(void)
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_LSE; | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@ -126,9 +127,11 @@ void SystemClock_Config(void)
Error_Handler(); Error_Handler();
} }
// Enable CSS for both clocks // CSS for HSE
HAL_RCC_EnableCSS(); HAL_RCC_EnableCSS();
// CSS for LSE
HAL_RCCEx_EnableLSECSS(); HAL_RCCEx_EnableLSECSS();
HAL_RCCEx_EnableLSECSS_IT();
} }
void Error_Handler(void) { void Error_Handler(void) {

15
firmware/targets/f4/Src/stm32wbxx_it.c
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@ -188,12 +188,12 @@ void SysTick_Handler(void)
*/ */
void TAMP_STAMP_LSECSS_IRQHandler(void) void TAMP_STAMP_LSECSS_IRQHandler(void)
{ {
/* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 0 */ if (!LL_RCC_LSE_IsReady()) {
HAL_RCC_CSSCallback(); // TODO: notify user about issue with LSE
/* USER CODE END TAMP_STAMP_LSECSS_IRQn 0 */ LL_RCC_ForceBackupDomainReset();
/* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 1 */ LL_RCC_ReleaseBackupDomainReset();
NVIC_SystemReset();
/* USER CODE END TAMP_STAMP_LSECSS_IRQn 1 */ }
} }
/** /**
@ -202,9 +202,6 @@ void TAMP_STAMP_LSECSS_IRQHandler(void)
void RCC_IRQHandler(void) void RCC_IRQHandler(void)
{ {
/* USER CODE BEGIN RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 0 */
if (!LL_RCC_LSE_IsReady()) {
HAL_RCC_CSSCallback();
}
/* USER CODE END RCC_IRQn 0 */ /* USER CODE END RCC_IRQn 0 */
/* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE BEGIN RCC_IRQn 1 */

3
firmware/targets/f4/api-hal/api-hal-power.c
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@ -15,8 +15,7 @@
volatile uint32_t api_hal_power_insomnia = 1; volatile uint32_t api_hal_power_insomnia = 1;
void HAL_RCC_CSSCallback(void) { void HAL_RCC_CSSCallback(void) {
LL_RCC_ForceBackupDomainReset(); // TODO: notify user about issue with HSE
LL_RCC_ReleaseBackupDomainReset();
NVIC_SystemReset(); NVIC_SystemReset();
} }

13
firmware/targets/f5/Src/main.c
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@ -73,11 +73,12 @@ void SystemClock_Config(void)
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
LL_RCC_HSE_SetCapacitorTuning(0x18); LL_RCC_HSE_SetCapacitorTuning(0x18);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_LSE; | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@ -127,9 +128,11 @@ void SystemClock_Config(void)
Error_Handler(); Error_Handler();
} }
// Enable CSS for both clocks // CSS for HSE
HAL_RCC_EnableCSS(); HAL_RCC_EnableCSS();
// CSS for LSE
HAL_RCCEx_EnableLSECSS(); HAL_RCCEx_EnableLSECSS();
HAL_RCCEx_EnableLSECSS_IT();
} }
void Error_Handler(void) { void Error_Handler(void) {

15
firmware/targets/f5/Src/stm32wbxx_it.c
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@ -188,12 +188,12 @@ void SysTick_Handler(void)
*/ */
void TAMP_STAMP_LSECSS_IRQHandler(void) void TAMP_STAMP_LSECSS_IRQHandler(void)
{ {
/* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 0 */ if (!LL_RCC_LSE_IsReady()) {
HAL_RCC_CSSCallback(); // TODO: notify user about issue with LSE
/* USER CODE END TAMP_STAMP_LSECSS_IRQn 0 */ LL_RCC_ForceBackupDomainReset();
/* USER CODE BEGIN TAMP_STAMP_LSECSS_IRQn 1 */ LL_RCC_ReleaseBackupDomainReset();
NVIC_SystemReset();
/* USER CODE END TAMP_STAMP_LSECSS_IRQn 1 */ }
} }
/** /**
@ -202,9 +202,6 @@ void TAMP_STAMP_LSECSS_IRQHandler(void)
void RCC_IRQHandler(void) void RCC_IRQHandler(void)
{ {
/* USER CODE BEGIN RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 0 */
if (!LL_RCC_LSE_IsReady()) {
HAL_RCC_CSSCallback();
}
/* USER CODE END RCC_IRQn 0 */ /* USER CODE END RCC_IRQn 0 */
/* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE BEGIN RCC_IRQn 1 */

3
firmware/targets/f5/api-hal/api-hal-power.c
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@ -15,8 +15,7 @@
volatile uint32_t api_hal_power_insomnia = 1; volatile uint32_t api_hal_power_insomnia = 1;
void HAL_RCC_CSSCallback(void) { void HAL_RCC_CSSCallback(void) {
LL_RCC_ForceBackupDomainReset(); // TODO: notify user about issue with HSE
LL_RCC_ReleaseBackupDomainReset();
NVIC_SystemReset(); NVIC_SystemReset();
} }