[FL-1146] GD0 self-test
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@@ -99,6 +99,63 @@ extern "C" {
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#define CC1101_PATABLE 0x3E /** PATABLE register number, an 8-byte table that defines the PA control settings */
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#define CC1101_FIFO 0x3F /** FIFO register nunmber, can be combined with CC1101_WRITE and/or CC1101_BURST */
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#define CC1101_IOCFG_INV (1<<6) /** IOCFG inversion */
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typedef enum {
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CC1101IocfgRxFifoThreshold=0x00,
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CC1101IocfgRxFifoThresholdOrPacket=0x01,
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CC1101IocfgTxFifoThreshold=0x02,
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CC1101IocfgTxFifoFull=0x03,
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CC1101IocfgRxOverflow=0x04,
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CC1101IocfgTxUnderflow=0x05,
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CC1101IocfgSyncWord=0x06,
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CC1101IocfgPacket=0x07,
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CC1101IocfgPreamble=0x08,
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CC1101IocfgClearChannel=0x09,
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CC1101IocfgLockDetector=0x0A,
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CC1101IocfgSerialClock=0x0B,
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CC1101IocfgSerialSynchronousDataOutput=0x0C,
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CC1101IocfgSerialDataOutput=0x0D,
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CC1101IocfgCarrierSense=0x0E,
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CC1101IocfgCrcOk=0x0F,
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/* Reserved range: 0x10 - 0x15 */
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CC1101IocfgRxHardData1=0x16,
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CC1101IocfgRxHardData0=0x17,
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/* Reserved range: 0x18 - 0x1A */
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CC1101IocfgPaPd=0x1B,
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CC1101IocfgLnaPd=0x1C,
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CC1101IocfgRxSymbolTick=0x1D,
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/* Reserved range: 0x1E - 0x23 */
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CC1101IocfgWorEvnt0=0x24,
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CC1101IocfgWorEvnt1=0x25,
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CC1101IocfgClk256=0x26,
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CC1101IocfgClk32k=0x27,
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/* Reserved: 0x28 */
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CC1101IocfgChpRdyN=0x29,
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/* Reserved: 0x2A */
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CC1101IocfgXoscStable=0x2B,
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/* Reserved range: 0x2C - 0x2D */
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CC1101IocfgHighImpedance=0x2E,
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CC1101IocfgHW=0x2F,
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/* Only one CC1101IocfgClkXoscN can be selected as an output at any time */
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CC1101IocfgClkXosc1=0x30,
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CC1101IocfgClkXosc1_5=0x31,
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CC1101IocfgClkXosc2=0x32,
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CC1101IocfgClkXosc3=0x33,
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CC1101IocfgClkXosc4=0x34,
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CC1101IocfgClkXosc6=0x35,
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CC1101IocfgClkXosc8=0x36,
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CC1101IocfgClkXosc12=0x37,
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CC1101IocfgClkXosc16=0x38,
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CC1101IocfgClkXosc24=0x39,
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CC1101IocfgClkXosc32=0x3A,
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CC1101IocfgClkXosc48=0x3B,
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CC1101IocfgClkXosc64=0x3C,
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CC1101IocfgClkXosc96=0x3D,
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CC1101IocfgClkXosc128=0x3E,
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CC1101IocfgClkXosc192=0x3F,
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} CC1101Iocfg;
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typedef enum {
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CC1101StateIDLE=0b000, /** IDLE state */
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CC1101StateRX=0b001, /** Receive mode */
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