76e3fd3060
* Firmware, Bootloader: add f3 target. Refactor code to be portable across targets. * Firmware: remove bkpt * Makefile: debug agent. Debug: f3 platform throw openocd. * freertos-openocd helper * separate hal resources * return of input_dump app * using hew target resources abstration layer for backlight and blink * dirty hack for input driver, f3 has no charging pin * worked input interrupts * working display * F3: switch to 32mHz resonator * F3: configure SD_CS pin * NFC: port to F3. * fat uart app * sd card hal api * separate CC1101 spi config * faster spi gpio for sd card * Assets: disable LFS * Cube: disable css on LSE * Input: format code * Make: add bootloader source code to formatting rule * F3: enable rf by default, adjust clock settings, map all pins where they should be. * libs for coreglitch_demo_0 * nvic priority * bus clocks all to 64 * lf-rfid timer and pin * irda * ir rx setup * tim2 irq handler * Makefile: environment aware mkdir * Makefile, Irukagotchi: commit seq number. * split falling and rising ir rx events * Makefile: proper git branch detect on old git. Firmware: api fix. * fix irda * Makefile,Irukagotchi: date timestamp. * NFC: adjust SPI speed * Irukagotchi: format code * Make: add blackmagic debug in host mode * Makefile: detach blackmagic from terminal signals * Makefile,Irukagotchi: stamp target * add F3 bootloader/firmware to CI Co-authored-by: Aleksandr Kutuzov <aku@plooks.com> Co-authored-by: DrZlo13 <who.just.the.doctor@gmail.com> Co-authored-by: aanper <mail@s3f.ru>
106 lines
2.7 KiB
INI
106 lines
2.7 KiB
INI
# script for stm32wbx family
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gdb_port 4242
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#
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# stm32wb devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32wbx
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} else {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
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# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
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# 2 WS compliant with VOS=Range1 and 24 MHz.
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mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
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mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 500
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE004203C 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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