144 lines
3.2 KiB
Markdown
Executable File
144 lines
3.2 KiB
Markdown
Executable File
## Level-to-pulser
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Finite state machine implementation of a device that takes a level
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change (low to high) and turns it into a one-period pulse.
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module levelToPulse(clk, in, out, reset);
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input clk, in, reset;
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output reg out;
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reg [1:0] state, next;
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// States
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parameter WAIT_LOW = 0;
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parameter WAIT_HIGH = 1;
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parameter RISING = 2; // I've just seen a rising edge
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parameter PULSE = 3; // I'm in the process of generating a pulse
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// Reset or update the state on every clock
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always @ (posedge clk or reset)
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begin
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if (reset)
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begin
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state <= WAIT_LOW;
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next <= WAIT_LOW;
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out = 0;
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end
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else
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state <= next;
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end
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// What to do in each state
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always @ (state or in) begin
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case (state)
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WAIT_LOW:
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begin
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if (in == 1)
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next = RISING;
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end
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RISING:
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begin
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out = 1;
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next = PULSE;
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end
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PULSE:
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begin
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out = 0;
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if (in == 0)
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next = WAIT_LOW;
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else
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next = WAIT_HIGH;
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end
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WAIT_HIGH:
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if (in == 0)
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next = WAIT_LOW;
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endcase // case (state)
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end
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endmodule
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## Level-to-pulser Testbench
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module test_stateMachine();
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// Parameters
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parameter CLKPERIOD = 20; // 50MHz at 1ns
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parameter FINISHTIME = 1000; // 1ms
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// DUT inputs
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reg clk, in, reset;
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// DUT outputs
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wire out;
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// DUT instantiation
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//
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levelToPulse DUT(clk, in, out, reset);
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// Stimulus
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// Clock generation
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always
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#(CLKPERIOD/2) clk = ~clk;
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// Initial conditions
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initial
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begin
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in = 0;
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clk = 1;
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reset = 0;
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// When at finishtime -- this shouldn't happen. It's just a safety.
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#FINISHTIME $display ("Reached the end of the sidewalk: %5d", $time);
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$finish;
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end
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// Inputs
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initial
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begin
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// Reset and wait
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#3 reset = 1;
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#3 reset = 0;
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repeat(5)
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#CLKPERIOD;
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// Go level high
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in = 1;
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repeat(5)
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#CLKPERIOD;
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// Go low
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in = 0;
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repeat(4)
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#CLKPERIOD;
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// Delay a short time so that input is in different phase with the clock
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#(CLKPERIOD / 2);
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in = 1;
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repeat(5)
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#CLKPERIOD;
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$display("-----------------------");
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$display("- Normal End at %5t -", $time);
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$display("-----------------------");
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$finish;
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end
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// Monitor
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initial
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begin
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$dumpfile ("test_stateMachine.lxt");
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$dumpvars(0, test_stateMachine);
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end
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endmodule
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[Category:FPGAWorkshop](Category:FPGAWorkshop "wikilink") |