110 lines
5.3 KiB
Markdown
Executable File
110 lines
5.3 KiB
Markdown
Executable File
- Download the Frequency Counter and Frequency Generator reference
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designs from
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<http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm>
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- Download the Picoblaze processor core from
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<http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm>
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- Unzip these projects & picoblaze source to your ~/Projects directory
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(or appropriatlely)
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- Implementing the projects directly
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- Each project comes with a .bit file that you can use to program the
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FPGA starter kit with. Use impact to program the chip.
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- On Windows, you can run the install batch scripts to run impact
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automatically.
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- Find a buddy with a board, and each of you program your respective
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boards. Grab an SMA cable and use that to check the output of the
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generator with the counter.
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- Implementing the projects through ISE
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- Implementing the frequency counter
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- In the frequency counter folder, there is a pdf. It is the readme
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for the project. It will be your friend - it details how to
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quickly run the project, setup the ISE project, design details for
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the hardware and picoblaze software, and some more project ideas.
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- In ISE, create a new design called "s3e_ref_freq_count" in your
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~/Projects directory.
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- Add the existing .vhd and .ucf sources from the frequency counter
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reference design folder that you unzipped
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- Add the existing .vhd source for kcpsm3.vhd from the picoblaze
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VHDL source folder
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- A portion of the design uses a undocumented mode of operation for
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the S3E DCM. Instructions for enabling this can be found in the
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dcm_fixed_osc.vhd file. In my experience, this breaks P&R (-will),
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and this should be removed in order to complete the design. The
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DCM is simply working in an free-running oscillator mode; this is
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merely used to provide a frequency source for testing and its
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removal will not adversely affect the design.
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- You'll need to modify the **frequency_counter.vhd** file in the
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project, to remove the instance of 'dcm_fixed_osc.vhd' from the
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design. We won't be doing anything in-depth with VHDL so don't
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be intimidated by the different language syntax.
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- You'll want to comment out the component dcm_fixed_osc (approx
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line 117) . In VHDL, comments are done with double hypens, --.
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- Commented out component
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<!-- -->
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--
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-- Fixed frequency oscillator using a DCM
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--
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--component dcm_fixed_osc
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-- port( clk_out : out std_logic;
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-- kick_start : in std_logic );
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-- end component;
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- - The instantiation of the dcm_fixed_osc needs to be commented out
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(approximately line 223)
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- Commented portion
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<!-- -->
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-- dcm_fixed_oscillator: dcm_fixed_osc
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-- port map ( clk_out => dcm_oscillator,
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-- kick_start => source_control(7) );
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- - Now we'll need to change the multiplexer. To keep the design nearly
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intact, we'll replicate the ring oscillator signal twice (approx
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line 245).
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- Changed multiplexer
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<!-- -->
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freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00")
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else clk_50mhz when (source_control(1 downto 0)="01")
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else ring_oscillator when (source_control(1 downto 0)="10")
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else ring_oscillator;
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- - Select the top level module, and take it through the implementation
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process - synthesis, place and route, generate programming file.
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- Use impact to program the .bit file to the FPGA! It should
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- - Implementing the frequency generator
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- In the frequency generator folder, there is a pdf. It is the
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readme for the project. It will be your friend - it details how to
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quickly run the project, setup the ISE project, design details for
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the hardware and picoblaze software, and some more project ideas.
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- In ISE, create a new design called "s3e_ref_freq_ref" in your
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~/Projects directory.
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- Add the existing .vhd and .ucf sources from the frequency ref
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reference design folder that you unzipped
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- Add the existing .vhd source for kcpsm3.vhd from the picoblaze
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VHDL source folder
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- A portion of the design uses a undocumented mode of operation for
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the S3E DCM. Instructions for enabling this can be found on page
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13 of the Frequency generator documentation. **The design will not
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work if the instructions are not followed!**
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- Afer this is done, you should be able to implement this design and
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program the FPGA with impact.
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- Things you can do!
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- You can use the .ucf file to move around the pin assignments. For
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instance, you can have the frequency counter read the clock input
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off of a stake or one of the pmod headers.3
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- Easy extension - create a second ring oscillator, called ring_osc2.
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You can extend the ring_osc.vhd for this purpose, adding additional
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delay stages will decrease the frequency generated. Follow a similar
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format, to the rest of the VHDL code, to declare the component,
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instantiation, a second ring_oscillator signal, and modify the
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multiplexer.
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- Once that is done, synthesis, P&R, and program the design. Select
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the second ring oscillator and see what its frequency is!
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- Look at the PDF's which come with the reference designs for more
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ideas!
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[Category:FPGAWorkshop](Category:FPGAWorkshop "wikilink") |