85 lines
2.2 KiB
Markdown
Executable File
85 lines
2.2 KiB
Markdown
Executable File
Placeholder...
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## Verilog Define Statements
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Verilog provides a text macro substitution facility. This may be useful
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for defining constants, opcodes, or with conditional compilation. To
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define a text macro, use the define keyword.
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`define myCode 13
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When you want to use the macro, simple use the macroname with a accent
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key.
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a = `myCode;
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The following compile directives are available for use
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`include Includes another file, avoid using pathnames
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`define Define a text macro
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`ifdef Starts conditional compilation, dependant on if a macro has been defined
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`else Alternate condiational compilation
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`endif Ends conditional compilation
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`ifndef Starts conditional compilation, like `ifdef
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`elseif Alternative conditional compilation
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The use of *\`define* doesn't require that the macro be given a value.
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This allows for the following code style (exceprt from a defines.v
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file).
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// Number of bits used for devider register. If used in system with
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// low frequency of system clock this can be reduced.
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// Use SPI_DIVIDER_LEN for fine tuning theexact number.
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//
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`define SPI_DIVIDER_LEN_8
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//`define SPI_DIVIDER_LEN_16
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//`define SPI_DIVIDER_LEN_24
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//`define SPI_DIVIDER_LEN_32
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`ifdef SPI_DIVIDER_LEN_8
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`define SPI_DIVIDER_LEN 5 // Can be set from 1 to 8
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`endif
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`ifdef SPI_DIVIDER_LEN_16
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`define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16
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`endif
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`ifdef SPI_DIVIDER_LEN_24
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`define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24
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`endif
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`ifdef SPI_DIVIDER_LEN_32
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`define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32
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`endif
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Likewise, conditional compilation of code is possible
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module add23(
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a,
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b,
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`ifdef ADD3
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c,
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`endif
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sum);
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output [3:0] sum;
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input [3:0] a, b;
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`ifdef ADD3
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input [3:0] c;
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`endif
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assign sum =
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`ifdef ADD3
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c+
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`endif
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a+b;
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endmodule
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## Verilog Events
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Lorem Ipsum
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## Verilog Tasks
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Lorem Ipsum
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[Category:FPGAWorkshop](Category:FPGAWorkshop "wikilink") |